linux-kernel - Re: [PATCH v2 0/8] Add support for StarFive VisionFive 2 Lite board

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Message-ID: <20251112-abroad-taps-a207a5850301@spud>
Date: Wed, 12 Nov 2025 14:36:54 +0000
From: Conor Dooley <conor@...nel.org>
To: Emil Renner Berthing <emil.renner.berthing@...onical.com>
Cc: Albert Ou <aou@...s.berkeley.edu>, Bjorn Helgaas <bhelgaas@...gle.com>,
	Conor Dooley <conor+dt@...nel.org>, E Shattow <e@...eshell.de>,
	Hal Feng <hal.feng@...rfivetech.com>,
	Heinrich Schuchardt <heinrich.schuchardt@...onical.com>,
	Krzysztof Kozlowski <krzk+dt@...nel.org>,
	Krzysztof Wilczyński <kwilczynski@...nel.org>,
	Lorenzo Pieralisi <lpieralisi@...nel.org>,
	Manivannan Sadhasivam <mani@...nel.org>,
	Palmer Dabbelt <palmer@...belt.com>, Paul Walmsley <pjw@...nel.org>,
	"Rafael J . Wysocki" <rafael@...nel.org>,
	Rob Herring <robh@...nel.org>,
	Viresh Kumar <viresh.kumar@...aro.org>, devicetree@...r.kernel.org,
	linux-riscv@...ts.infradead.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH v2 0/8] Add support for StarFive VisionFive 2 Lite board

On Wed, Nov 12, 2025 at 05:54:09AM -0800, Emil Renner Berthing wrote:
> Quoting Hal Feng (2025-11-07 10:55:22)
> > VisionFive 2 Lite is a mini SBC based on the StarFive JH7110S industrial
> > SoC which can run at -40~85 degrees centigrade and up to 1.25GHz.
> >
> > Board features:
> > - JH7110S SoC
> > - 4/8 GiB LPDDR4 DRAM
> > - AXP15060 PMIC
> > - 40 pin GPIO header
> > - 1x USB 3.0 host port
> > - 3x USB 2.0 host port
> > - 1x M.2 M-Key (size: 2242)
> > - 1x MicroSD slot (optional non-removable 64GiB eMMC)
> > - 1x QSPI Flash
> > - 1x I2C EEPROM
> > - 1x 1Gbps Ethernet port
> > - SDIO-based Wi-Fi & UART-based Bluetooth
> > - 1x HDMI port
> > - 1x 2-lane DSI
> > - 1x 2-lane CSI
> >
> > VisionFive 2 Lite schematics: https://doc-en.rvspace.org/VisionFive2Lite/PDF/VF2_LITE_V1.10_TF_20250818_SCH.pdf
> > VisionFive 2 Lite Quick Start Guide: https://doc-en.rvspace.org/VisionFive2Lite/VisionFive2LiteQSG/index.html
> > More documents: https://doc-en.rvspace.org/Doc_Center/visionfive_2_lite.html
> 
> 
> Hi Hal,
> 
> Currently the JH7110 device trees are layed out like this, with a nice
> separation between the SoC description and board descriptions:
> 
> jh7110.dtsi               # JH7110 SoC description
> |- jh7110-common.dtsi     # Peripherals common to all JH7110 boards
>    |- jh7110-starfive-visionfive-2.dtsi # Peripherals common to VF2 boards
>    |  |- <VF2 boards>     # Final VF2 board descriptions
>    |- jh7110-milkv-marscm.dtsi # Peripherals common to Mars CM boards
>    |  |- <Mars CM boards> # Final Mars CM board descriptions
>    |- <other boards>      # Other JH7110 board descriptions
> 
> With this series it moves to
> 
> jh711x.dtsi

Now that you notice it, why does this have an x to begin with, when both
users have jh7110 in them? Wouldn't to just be jh7110.dtsi for both?

> |- jh711x-common.dtsi
>    |- jh7110-common.dtsi
>    |  |- <jh7110 boards>
>    |- jh7110s-common.dtsi
>       |- <jh7110s boards>

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