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Message-ID: <20251112-upstream_uboot_properties-v1-4-0b19133710e3@foss.st.com>
Date: Wed, 12 Nov 2025 11:46:46 +0100
From: Patrice Chotard <patrice.chotard@...s.st.com>
To: Rob Herring <robh@...nel.org>, Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>,
Maxime Coquelin
<mcoquelin.stm32@...il.com>,
Alexandre Torgue <alexandre.torgue@...s.st.com>,
Patrick Delaunay <patrick.delaunay@...s.st.com>
CC: <devicetree@...r.kernel.org>, <linux-stm32@...md-mailman.stormreply.com>,
<linux-arm-kernel@...ts.infradead.org>, <linux-kernel@...r.kernel.org>,
Patrice Chotard <patrice.chotard@...s.st.com>
Subject: [PATCH 4/6] ARM: dts: stm32: Add boot phase tags for
STMicroelectronics mp13 boards
The bootph-all flag was introduced in dt-schema
(dtschema/schemas/bootph.yaml) to define node usage across
different boot phases.
To ensure SD boot, timer, gpio, syscfg, clock and uart nodes need to be
present in all boot stages, so add missing bootph-all phase flag
to these nodes to support SD boot.
Signed-off-by: Patrice Chotard <patrice.chotard@...s.st.com>
---
arch/arm/boot/dts/st/stm32mp131.dtsi | 21 +++++++++++++++++++++
arch/arm/boot/dts/st/stm32mp135f-dk.dts | 11 +++++++++++
2 files changed, 32 insertions(+)
diff --git a/arch/arm/boot/dts/st/stm32mp131.dtsi b/arch/arm/boot/dts/st/stm32mp131.dtsi
index fd730aa37c22..26c3b5529582 100644
--- a/arch/arm/boot/dts/st/stm32mp131.dtsi
+++ b/arch/arm/boot/dts/st/stm32mp131.dtsi
@@ -35,6 +35,7 @@ optee {
compatible = "linaro,optee-tz";
interrupt-parent = <&intc>;
interrupts = <GIC_PPI 15 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
+ bootph-all;
};
scmi: scmi {
@@ -42,15 +43,18 @@ scmi: scmi {
#address-cells = <1>;
#size-cells = <0>;
linaro,optee-channel-id = <0>;
+ bootph-all;
scmi_clk: protocol@14 {
reg = <0x14>;
#clock-cells = <1>;
+ bootph-all;
};
scmi_reset: protocol@16 {
reg = <0x16>;
#reset-cells = <1>;
+ bootph-all;
};
scmi_voltd: protocol@17 {
@@ -88,6 +92,7 @@ intc: interrupt-controller@...21000 {
psci {
compatible = "arm,psci-1.0";
method = "smc";
+ bootph-some-ram;
};
timer {
@@ -131,6 +136,7 @@ soc {
#size-cells = <1>;
interrupt-parent = <&intc>;
ranges;
+ bootph-all;
timers2: timer@...00000 {
#address-cells = <1>;
@@ -791,6 +797,7 @@ rcc: rcc@...00000 {
<&scmi_clk CK_SCMI_CSI>,
<&scmi_clk CK_SCMI_LSE>,
<&scmi_clk CK_SCMI_LSI>;
+ bootph-all;
};
pwr_regulators: pwr@...01000 {
@@ -900,6 +907,7 @@ syscfg: syscon@...20000 {
compatible = "st,stm32mp157-syscfg", "syscon";
reg = <0x50020000 0x400>;
clocks = <&rcc SYSCFG>;
+ bootph-all;
};
lptimer4: timer@...23000 {
@@ -1003,6 +1011,7 @@ iwdg2: watchdog@...02000 {
clocks = <&rcc IWDG2>, <&scmi_clk CK_SCMI_LSI>;
clock-names = "pclk", "lsi";
status = "disabled";
+ bootph-all;
};
rtc: rtc@...04000 {
@@ -1020,6 +1029,7 @@ bsec: efuse@...05000 {
reg = <0x5c005000 0x400>;
#address-cells = <1>;
#size-cells = <1>;
+ bootph-all;
part_number_otp: part_number_otp@4 {
reg = <0x4 0x2>;
@@ -1646,6 +1656,7 @@ usbphyc: usbphyc@...06000 {
vdda1v8-supply = <&scmi_reg18>;
access-controllers = <&etzpc 5>;
status = "disabled";
+ bootph-all;
usbphyc_port0: usb-phy@0 {
#phy-cells = <0>;
@@ -1670,6 +1681,7 @@ pinctrl: pinctrl@...02000 {
ranges = <0 0x50002000 0x8400>;
interrupt-parent = <&exti>;
st,syscfg = <&exti 0x60 0xff>;
+ bootph-all;
gpioa: gpio@...02000 {
gpio-controller;
@@ -1681,6 +1693,7 @@ gpioa: gpio@...02000 {
st,bank-name = "GPIOA";
ngpios = <16>;
gpio-ranges = <&pinctrl 0 0 16>;
+ bootph-all;
};
gpiob: gpio@...03000 {
@@ -1693,6 +1706,7 @@ gpiob: gpio@...03000 {
st,bank-name = "GPIOB";
ngpios = <16>;
gpio-ranges = <&pinctrl 0 16 16>;
+ bootph-all;
};
gpioc: gpio@...04000 {
@@ -1705,6 +1719,7 @@ gpioc: gpio@...04000 {
st,bank-name = "GPIOC";
ngpios = <16>;
gpio-ranges = <&pinctrl 0 32 16>;
+ bootph-all;
};
gpiod: gpio@...05000 {
@@ -1717,6 +1732,7 @@ gpiod: gpio@...05000 {
st,bank-name = "GPIOD";
ngpios = <16>;
gpio-ranges = <&pinctrl 0 48 16>;
+ bootph-all;
};
gpioe: gpio@...06000 {
@@ -1729,6 +1745,7 @@ gpioe: gpio@...06000 {
st,bank-name = "GPIOE";
ngpios = <16>;
gpio-ranges = <&pinctrl 0 64 16>;
+ bootph-all;
};
gpiof: gpio@...07000 {
@@ -1741,6 +1758,7 @@ gpiof: gpio@...07000 {
st,bank-name = "GPIOF";
ngpios = <16>;
gpio-ranges = <&pinctrl 0 80 16>;
+ bootph-all;
};
gpiog: gpio@...08000 {
@@ -1753,6 +1771,7 @@ gpiog: gpio@...08000 {
st,bank-name = "GPIOG";
ngpios = <16>;
gpio-ranges = <&pinctrl 0 96 16>;
+ bootph-all;
};
gpioh: gpio@...09000 {
@@ -1765,6 +1784,7 @@ gpioh: gpio@...09000 {
st,bank-name = "GPIOH";
ngpios = <15>;
gpio-ranges = <&pinctrl 0 112 15>;
+ bootph-all;
};
gpioi: gpio@...0a000 {
@@ -1777,6 +1797,7 @@ gpioi: gpio@...0a000 {
st,bank-name = "GPIOI";
ngpios = <8>;
gpio-ranges = <&pinctrl 0 128 8>;
+ bootph-all;
};
};
};
diff --git a/arch/arm/boot/dts/st/stm32mp135f-dk.dts b/arch/arm/boot/dts/st/stm32mp135f-dk.dts
index 9764a6bfa5b4..a05d458c9b37 100644
--- a/arch/arm/boot/dts/st/stm32mp135f-dk.dts
+++ b/arch/arm/boot/dts/st/stm32mp135f-dk.dts
@@ -517,9 +517,20 @@ &uart4 {
pinctrl-2 = <&uart4_idle_pins_a>;
/delete-property/dmas;
/delete-property/dma-names;
+ bootph-all;
status = "okay";
};
+&uart4_pins_a {
+ bootph-all;
+ pins1 {
+ bootph-all;
+ };
+ pins2 {
+ bootph-all;
+ };
+};
+
&uart8 {
pinctrl-names = "default", "sleep", "idle";
pinctrl-0 = <&uart8_pins_a>;
--
2.43.0
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