lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID:
 <TY3PR01MB11346CB74E94956AC93A9471C86CDA@TY3PR01MB11346.jpnprd01.prod.outlook.com>
Date: Thu, 13 Nov 2025 19:34:49 +0000
From: Biju Das <biju.das.jz@...renesas.com>
To: geert <geert@...ux-m68k.org>
CC: Michael Turquette <mturquette@...libre.com>, Stephen Boyd
	<sboyd@...nel.org>, "linux-renesas-soc@...r.kernel.org"
	<linux-renesas-soc@...r.kernel.org>, "linux-clk@...r.kernel.org"
	<linux-clk@...r.kernel.org>, "linux-kernel@...r.kernel.org"
	<linux-kernel@...r.kernel.org>, Prabhakar Mahadev Lad
	<prabhakar.mahadev-lad.rj@...renesas.com>, biju.das.au
	<biju.das.au@...il.com>
Subject: RE: [PATCH 01/19] clk: renesas: r9a09g047: Add RSCI clocks/resets

Hi Geert,

Thanks for the feedback.

> -----Original Message-----
> From: Geert Uytterhoeven <geert@...ux-m68k.org>
> Sent: 13 November 2025 18:20
> Subject: Re: [PATCH 01/19] clk: renesas: r9a09g047: Add RSCI clocks/resets
> 
> Hi Biju,
> 
> On Mon, 27 Oct 2025 at 16:46, Biju Das <biju.das.jz@...renesas.com> wrote:
> > Add RSCI clock and reset entries.
> >
> > Signed-off-by: Biju Das <biju.das.jz@...renesas.com>
> 
> Thanks for your patch!
> 
> > --- a/drivers/clk/renesas/r9a09g047-cpg.c
> > +++ b/drivers/clk/renesas/r9a09g047-cpg.c
> > @@ -218,6 +224,106 @@ static const struct rzv2h_mod_clk r9a09g047_mod_clks[] __initconst = {
> >                                                 BUS_MSTOP(5, BIT(13))),
> >         DEF_MOD("wdt_3_clk_loco",               CLK_QEXTAL, 5, 2, 2, 18,
> >                                                 BUS_MSTOP(5,
> > BIT(13))),
> > +       DEF_MOD("rsci0_pclk",                   CLK_PLLCM33_DIV16, 5, 13, 2, 29,
> > +                                               BUS_MSTOP(11, BIT(3))),
> > +       DEF_MOD("rsci0_tclk",                   CLK_PLLCM33_DIV16, 5, 14, 2, 30,
> > +                                               BUS_MSTOP(11,
> > + BIT(3))),
> 
> According to both the clock list and the clock system diagram, the parent clock of rsciN_pclk and
> rsciN_tclk is CLK_PLLCLN_DIV16?

Thanks, you are correct, I will fix this in next version.

Cheers,
Biju

> 
> The rest LGTM, so with the above clarified:
> Reviewed-by: Geert Uytterhoeven <geert+renesas@...der.be>
> 
> Gr{oetje,eeting}s,
> 
>                         Geert
> 
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@...ux-m68k.org
> 
> In personal conversations with technical people, I call myself a hacker. But when I'm talking to
> journalists I just say "programmer" or something like that.
>                                 -- Linus Torvalds

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ