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Message-ID: <bmzzuk4zvxyso5qyw7lsq3dxc7roiqhnip2mwsrlwkeenna7ic@n6cpil6nmahx>
Date: Fri, 14 Nov 2025 23:10:18 +0530
From: Manivannan Sadhasivam <mani@...nel.org>
To: hans.zhang@...tech.com
Cc: bhelgaas@...gle.com, helgaas@...nel.org, lpieralisi@...nel.org, 
	kw@...ux.com, robh@...nel.org, kwilczynski@...nel.org, krzk+dt@...nel.org, 
	conor+dt@...nel.org, mpillai@...ence.com, fugang.duan@...tech.com, 
	guoyin.chen@...tech.com, peter.chen@...tech.com, cix-kernel-upstream@...tech.com, 
	linux-pci@...r.kernel.org, devicetree@...r.kernel.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH v11 09/10] arm64: dts: cix: Add PCIe Root Complex on sky1

On Sat, Nov 08, 2025 at 10:03:04PM +0800, hans.zhang@...tech.com wrote:
> From: Hans Zhang <hans.zhang@...tech.com>
> 
> Add pcie_x*_rc node to support Sky1 PCIe driver based on the
> Cadence PCIe core.
> 
> Supports Gen1/Gen2/Gen3/Gen4, 1/2/4/8 lane, MSI/MSI-x interrupts
> using the ARM GICv3.
> 
> Signed-off-by: Hans Zhang <hans.zhang@...tech.com>

Acked-by: Manivannan Sadhasivam <mani@...nel.org>

- Mani

> ---
>  arch/arm64/boot/dts/cix/sky1.dtsi | 126 ++++++++++++++++++++++++++++++
>  1 file changed, 126 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/cix/sky1.dtsi b/arch/arm64/boot/dts/cix/sky1.dtsi
> index 2fb2c99c0796..1abafbfc3c9b 100644
> --- a/arch/arm64/boot/dts/cix/sky1.dtsi
> +++ b/arch/arm64/boot/dts/cix/sky1.dtsi
> @@ -388,6 +388,132 @@ mbox_ap2sfh: mailbox@...0000 {
>  			cix,mbox-dir = "tx";
>  		};
>  
> +		pcie_x8_rc: pcie@...0000 {
> +			compatible = "cix,sky1-pcie-host";
> +			reg = <0x00 0x0a010000 0x00 0x10000>,
> +			      <0x00 0x2c000000 0x00 0x4000000>,
> +			      <0x00 0x0a000300 0x00 0x100>,
> +			      <0x00 0x0a000400 0x00 0x100>,
> +			      <0x00 0x60000000 0x00 0x00100000>;
> +			reg-names = "reg", "cfg", "rcsu_strap", "rcsu_status", "msg";
> +			ranges = <0x01000000 0x0 0x60100000 0x0 0x60100000 0x0 0x00100000>,
> +				 <0x02000000 0x0 0x60200000 0x0 0x60200000 0x0 0x1fe00000>,
> +				 <0x43000000 0x18 0x00000000 0x18 0x00000000 0x04 0x00000000>;
> +			#address-cells = <3>;
> +			#size-cells = <2>;
> +			bus-range = <0xc0 0xff>;
> +			device_type = "pci";
> +			#interrupt-cells = <1>;
> +			interrupt-map-mask = <0 0 0 0x7>;
> +			interrupt-map = <0 0 0 1 &gic 0 0 GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH 0>,
> +					<0 0 0 2 &gic 0 0 GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH 0>,
> +					<0 0 0 3 &gic 0 0 GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH 0>,
> +					<0 0 0 4 &gic 0 0 GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH 0>;
> +			msi-map = <0xc000 &gic_its 0xc000 0x4000>;
> +			status = "disabled";
> +		};
> +
> +		pcie_x4_rc: pcie@...0000 {
> +			compatible = "cix,sky1-pcie-host";
> +			reg = <0x00 0x0a070000 0x00 0x10000>,
> +			      <0x00 0x29000000 0x00 0x3000000>,
> +			      <0x00 0x0a060300 0x00 0x40>,
> +			      <0x00 0x0a060400 0x00 0x40>,
> +			      <0x00 0x50000000 0x00 0x00100000>;
> +			reg-names = "reg", "cfg", "rcsu_strap", "rcsu_status", "msg";
> +			ranges = <0x01000000 0x00 0x50100000 0x00 0x50100000 0x00 0x00100000>,
> +				 <0x02000000 0x00 0x50200000 0x00 0x50200000 0x00 0x0fe00000>,
> +				 <0x43000000 0x14 0x00000000 0x14 0x00000000 0x04 0x00000000>;
> +			#address-cells = <3>;
> +			#size-cells = <2>;
> +			bus-range = <0x90 0xbf>;
> +			device_type = "pci";
> +			#interrupt-cells = <1>;
> +			interrupt-map-mask = <0 0 0 0x7>;
> +			interrupt-map = <0 0 0 1 &gic 0 0 GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH 0>,
> +					<0 0 0 2 &gic 0 0 GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH 0>,
> +					<0 0 0 3 &gic 0 0 GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH 0>,
> +					<0 0 0 4 &gic 0 0 GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH 0>;
> +			msi-map = <0x9000 &gic_its 0x9000 0x3000>;
> +			status = "disabled";
> +		};
> +
> +		pcie_x2_rc: pcie@...0000 {
> +			compatible = "cix,sky1-pcie-host";
> +			reg = <0x00 0x0a0c0000 0x00 0x10000>,
> +			      <0x00 0x26000000 0x00 0x3000000>,
> +			      <0x00 0x0a0600340 0x00 0x20>,
> +			      <0x00 0x0a0600440 0x00 0x20>,
> +			      <0x00 0x40000000 0x00 0x00100000>;
> +			reg-names = "reg", "cfg", "rcsu_strap", "rcsu_status", "msg";
> +			ranges = <0x01000000 0x0 0x40100000 0x0 0x40100000 0x0 0x00100000>,
> +				 <0x02000000 0x0 0x40200000 0x0 0x40200000 0x0 0x0fe00000>,
> +				 <0x43000000 0x10 0x00000000 0x10 0x00000000 0x04 0x00000000>;
> +			#address-cells = <3>;
> +			#size-cells = <2>;
> +			bus-range = <0x60 0x8f>;
> +			device_type = "pci";
> +			#interrupt-cells = <1>;
> +			interrupt-map-mask = <0 0 0 0x7>;
> +			interrupt-map = <0 0 0 1 &gic 0 0 GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH 0>,
> +					<0 0 0 2 &gic 0 0 GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH 0>,
> +					<0 0 0 3 &gic 0 0 GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH 0>,
> +					<0 0 0 4 &gic 0 0 GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH 0>;
> +			msi-map = <0x6000 &gic_its 0x6000 0x3000>;
> +			status = "disabled";
> +		};
> +
> +		pcie_x1_0_rc: pcie@...0000 {
> +			compatible = "cix,sky1-pcie-host";
> +			reg = <0x00 0x0a0d0000 0x00 0x10000>,
> +			      <0x00 0x20000000 0x00 0x3000000>,
> +			      <0x00 0x0a060360 0x00 0x20>,
> +			      <0x00 0x0a060460 0x00 0x20>,
> +			      <0x00 0x30000000 0x00 0x00100000>;
> +			reg-names = "reg", "cfg", "rcsu_strap", "rcsu_status", "msg";
> +			ranges = <0x01000000 0x0 0x30100000 0x0 0x30100000 0x0 0x00100000>,
> +				 <0x02000000 0x0 0x30200000 0x0 0x30200000 0x0 0x07e00000>,
> +				 <0x43000000 0x08 0x00000000 0x08 0x00000000 0x04 0x00000000>;
> +			#address-cells = <3>;
> +			#size-cells = <2>;
> +			bus-range = <0x00 0x2f>;
> +			device_type = "pci";
> +			#interrupt-cells = <1>;
> +			interrupt-map-mask = <0 0 0 0x7>;
> +			interrupt-map = <0 0 0 1 &gic 0 0 GIC_SPI 436 IRQ_TYPE_LEVEL_HIGH 0>,
> +					<0 0 0 2 &gic 0 0 GIC_SPI 437 IRQ_TYPE_LEVEL_HIGH 0>,
> +					<0 0 0 3 &gic 0 0 GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH 0>,
> +					<0 0 0 4 &gic 0 0 GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH 0>;
> +			msi-map = <0x0000 &gic_its 0x0000 0x3000>;
> +			status = "disabled";
> +		};
> +
> +		pcie_x1_1_rc: pcie@...0000 {
> +			compatible = "cix,sky1-pcie-host";
> +			reg = <0x00 0x0a0e0000 0x00 0x10000>,
> +			      <0x00 0x23000000 0x00 0x3000000>,
> +			      <0x00 0x0a060380 0x00 0x20>,
> +			      <0x00 0x0a060480 0x00 0x20>,
> +			      <0x00 0x38000000 0x00 0x00100000>;
> +			reg-names = "reg", "cfg", "rcsu_strap", "rcsu_status", "msg";
> +			ranges = <0x01000000 0x0 0x38100000 0x0 0x38100000 0x0 0x00100000>,
> +				 <0x02000000 0x0 0x38200000 0x0 0x38200000 0x0 0x07e00000>,
> +				 <0x43000000 0x0C 0x00000000 0x0C 0x00000000 0x04 0x00000000>;
> +			#address-cells = <3>;
> +			#size-cells = <2>;
> +			bus-range = <0x30 0x5f>;
> +			device_type = "pci";
> +
> +			#interrupt-cells = <1>;
> +			interrupt-map-mask = <0 0 0 0x7>;
> +			interrupt-map = <0 0 0 1 &gic 0 0 GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH 0>,
> +					<0 0 0 2 &gic 0 0 GIC_SPI 446 IRQ_TYPE_LEVEL_HIGH 0>,
> +					<0 0 0 3 &gic 0 0 GIC_SPI 447 IRQ_TYPE_LEVEL_HIGH 0>,
> +					<0 0 0 4 &gic 0 0 GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH 0>;
> +			msi-map = <0x3000 &gic_its 0x3000 0x3000>;
> +			status = "disabled";
> +		};
> +
>  		gic: interrupt-controller@...0000 {
>  			compatible = "arm,gic-v3";
>  			reg = <0x0 0x0e010000 0 0x10000>,	/* GICD */
> -- 
> 2.49.0
> 

-- 
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