linux-kernel - Re: [PATCH v5 44/44] KVM: x86/pmu: Elide WRMSRs when loading guest PMCs if values already match

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Message-ID: <780ec006-ca77-40bc-ae9e-8ed0ec093dc5@amd.com>
Date: Fri, 14 Nov 2025 11:49:30 +0530
From: Manali Shukla <manali.shukla@....com>
To: Sean Christopherson <seanjc@...gle.com>, Marc Zyngier <maz@...nel.org>,
	Oliver Upton <oliver.upton@...ux.dev>, Tianrui Zhao
	<zhaotianrui@...ngson.cn>, Bibo Mao <maobibo@...ngson.cn>, Huacai Chen
	<chenhuacai@...nel.org>, Anup Patel <anup@...infault.org>, Paul Walmsley
	<paul.walmsley@...ive.com>, Palmer Dabbelt <palmer@...belt.com>, Albert Ou
	<aou@...s.berkeley.edu>, Xin Li <xin@...or.com>, "H. Peter Anvin"
	<hpa@...or.com>, Andy Lutomirski <luto@...nel.org>, Peter Zijlstra
	<peterz@...radead.org>, Ingo Molnar <mingo@...hat.com>, "Arnaldo Carvalho de
 Melo" <acme@...nel.org>, Namhyung Kim <namhyung@...nel.org>, Paolo Bonzini
	<pbonzini@...hat.com>
CC: <linux-arm-kernel@...ts.infradead.org>, <kvmarm@...ts.linux.dev>,
	<kvm@...r.kernel.org>, <loongarch@...ts.linux.dev>,
	<kvm-riscv@...ts.infradead.org>, <linux-riscv@...ts.infradead.org>,
	<linux-kernel@...r.kernel.org>, <linux-perf-users@...r.kernel.org>, Kan Liang
	<kan.liang@...ux.intel.com>, Yongwei Ma <yongwei.ma@...el.com>, Mingwei Zhang
	<mizhang@...gle.com>, Xiong Zhang <xiong.y.zhang@...ux.intel.com>, "Sandipan
 Das" <sandipan.das@....com>, Dapeng Mi <dapeng1.mi@...ux.intel.com>
Subject: Re: [PATCH v5 44/44] KVM: x86/pmu: Elide WRMSRs when loading guest
 PMCs if values already match

On 8/7/2025 1:27 AM, Sean Christopherson wrote:
> When loading a mediated PMU state, elide the WRMSRs to load PMCs with the
> guest's value if the value in hardware already matches the guest's value.
> For the relatively common case where neither the guest nor the host is
> actively using the PMU, i.e. when all/many counters are '0', eliding the
> WRMSRs reduces the latency of handling VM-Exit by a measurable amount
> (WRMSR is significantly more expensive than RDPMC).
> 
> As measured by KVM-Unit-Tests' CPUID VM-Exit testcase, this provides a
> a ~25% reduction in latency (4k => 3k cycles) on Intel Emerald Rapids,
> and a ~13% reduction (6.2k => 5.3k cycles) on AMD Turing.

Nit. s/AMD Turing/AMD Turin

-Manali
> 
> Signed-off-by: Sean Christopherson <seanjc@...gle.com>