linux-kernel - Re: [PATCH v2 2/2] arm64: dts: qcom: Add support for Pixel 3 and Pixel 3 XL

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Message-ID: <f15c4ed1-5997-48a1-a0a1-1b0113645517@ixit.cz>
Date: Mon, 17 Nov 2025 19:35:00 +0100
From: David Heidelberg <david@...t.cz>
To: Konrad Dybcio <konrad.dybcio@....qualcomm.com>,
 Bjorn Andersson <andersson@...nel.org>,
 Konrad Dybcio <konradybcio@...nel.org>, Rob Herring <robh@...nel.org>,
 Krzysztof Kozlowski <krzk+dt@...nel.org>, Conor Dooley <conor+dt@...nel.org>
Cc: phodina@...tonmail.com, linux-arm-msm@...r.kernel.org,
 devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
 phone-devel@...r.kernel.org, Amit Pundir <amit.pundir@...aro.org>,
 Casey Connolly <casey@...nolly.tech>, Joel Selvaraj <foss@...lselvaraj.com>,
 Sumit Semwal <sumit.semwal@...aro.org>, Vinod Koul <vkoul@...nel.org>
Subject: Re: [PATCH v2 2/2] arm64: dts: qcom: Add support for Pixel 3 and
 Pixel 3 XL

On 30/10/2025 13:10, Konrad Dybcio wrote:
> On 10/30/25 1:03 PM, David Heidelberg wrote:
>> On 30/10/2025 12:32, Konrad Dybcio wrote:
>>> On 10/30/25 8:24 AM, David Heidelberg via B4 Relay wrote:
>>>> From: David Heidelberg <david@...t.cz>
> 
> [...]
> 
>>>> +    battery: battery {
>>>> +        compatible = "simple-battery";
>>>> +
>>>> +        status = "disabled";
>>>
>>> You added support for both non-proto boards based on this platform,
>>> there is no usecase for you to disable the battery, remove this line
>>
>> Should I keep the status = "okay" in the board files or drop it too?
> 
> Drop it, nodes are enabled unless they're explicitly disabled
> 
> [...]
> 
>>>> +&tlmm {
>>>> +    gpio-reserved-ranges = <0 4>, <81 4>;
>>>
>>> Could you add a comment (like in x1-crd.dtsi) mentioning what these
>>> pins correspond to? Usually it's a fingerprint scanner or things like
>>> that
>>
>> Sure, I looked into it, but I haven't found (so far) information about the assigned blocks. In next revision it'll be addressed :)>
> 
> Thanks, you can usually correlate them to a QUP instance based on the pinctrl

For now I verified that 0 - 4 is SPI (Intel MNH Pixel Visual Core), but 
81 - 84 is at best educated guess SPI (Fingerprint Cards FPC1075).

The information about 81 - 84 are generally nowhere to be found.

The downstream device-tree

qupv3_se15_spi: spi@...000

thou it's disabled, so I assume there is external properietary 
user-space driver handling all of this.

I could fill the guess, if that's good enough.

David

> 
> Konrad

-- 
David Heidelberg