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Message-ID: <a9bdc5cb-28f2-4d0b-a823-4039fdaf0aa1@redhat.com>
Date: Mon, 17 Nov 2025 14:58:30 -0500
From: Waiman Long <llong@...hat.com>
To: Borislav Petkov <bp@...en8.de>
Cc: Thomas Gleixner <tglx@...utronix.de>, Ingo Molnar <mingo@...hat.com>,
Dave Hansen <dave.hansen@...ux.intel.com>, "H. Peter Anvin" <hpa@...or.com>,
x86@...nel.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH tip] x86/microcode/AMD: Read from MSR_AMD64_PATCH_LEVEL to
get base_rev if not defined
On 11/17/25 2:37 PM, Borislav Petkov wrote:
> On Mon, Nov 17, 2025 at 02:15:27PM -0500, Waiman Long wrote:
>> AMD microcode is being handled inconsistenly depending on whether the
>> CONFIG_MICROCODE_DBG is on or off.
> Did you read the help text to CONFIG_MICROCODE_DBG?
>
I am fine if "microcode,base_rev=" is specified in the boot command line
to force a base_rev for testing purpose. But if that is not specified,
get_patch_level() should return the right value. The problem I have on
that particular test machine mentioned in the commit is that the kernel
is trying to load an incompatible microcode blob causing error like the
following when CONFIG_MICROCODE_DBG is on.
[ 0.000000] unchecked MSR access error: WRMSR to 0xc0010020 (tried to
write 0xff11000026d3e740) at rIP: 0xffffffffa72cc63b
(__apply_microcode_amd+0x3b/0xb0)
[ 0.000000] Call Trace:
[ 0.000000] <TASK>
[ 0.000000] ? show_trace_log_lvl+0x1b0/0x2f0
[ 0.000000] ? show_trace_log_lvl+0x1b0/0x2f0
[ 0.000000] ? ex_handler_msr.isra.0.cold+0x5b/0x60
[ 0.000000] ? fixup_exception+0x8f/0x380
[ 0.000000] ? early_fixup_exception+0x45/0xb0
[ 0.000000] ? early_idt_handler_common+0x2f/0x3a
[ 0.000000] ? __apply_microcode_amd+0x3b/0xb0
[ 0.000000] ? load_ucode_amd_bsp+0x10b/0x140
[ 0.000000] ? x86_64_start_kernel+0x84/0xa0
[ 0.000000] ? common_startup_64+0x13e/0x141
[ 0.000000] </TASK>
[ 0.000000] microcode: updated rev: 0xa101148
I can add a boot_cpu_has(X86_FEATURE_HYPERVISOR) check and use
native_rdmsr() only if there is no hypervisor running. Do you think that
is acceptable?
Regards,
Longman
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