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Message-Id: <20251118074055.2523766-4-xu.yang_2@nxp.com>
Date: Tue, 18 Nov 2025 15:40:55 +0800
From: Xu Yang <xu.yang_2@....com>
To: robh@...nel.org,
krzk+dt@...nel.org,
conor+dt@...nel.org,
shawnguo@...nel.org,
s.hauer@...gutronix.de,
kernel@...gutronix.de,
festevam@...il.com,
abelvesa@...nel.org,
peng.fan@....com,
mturquette@...libre.com,
sboyd@...nel.org,
Frank.Li@....com,
hongxing.zhu@....com
Cc: devicetree@...r.kernel.org,
imx@...ts.linux.dev,
jun.li@....com,
linux-arm-kernel@...ts.infradead.org,
linux-kernel@...r.kernel.org,
linux-clk@...r.kernel.org
Subject: [PATCH 4/4] arm64: dts: imx95: fix hsio_blk_ctl reg map
The HSIO block control register map should be 0x4c010000~0x4c01FFFF.
Correct the start address and set length to 0x100 for available
registers.
Fixes: 3c8d7b5d2bed ("arm64: dts: imx95: add ref clock for pcie nodes")
Cc: stable@...r.kernel.org
Signed-off-by: Xu Yang <xu.yang_2@....com>
---
arch/arm64/boot/dts/freescale/imx95.dtsi | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/imx95.dtsi b/arch/arm64/boot/dts/freescale/imx95.dtsi
index 1292677cbe4e..21c9df445be0 100644
--- a/arch/arm64/boot/dts/freescale/imx95.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx95.dtsi
@@ -1774,9 +1774,9 @@ usb3_dwc3: usb@...00000 {
};
};
- hsio_blk_ctl: syscon@...100c0 {
+ hsio_blk_ctl: syscon@...10000 {
compatible = "nxp,imx95-hsio-blk-ctl", "syscon";
- reg = <0x0 0x4c0100c0 0x0 0x1>;
+ reg = <0x0 0x4c010000 0x0 0x100>;
#clock-cells = <1>;
clocks = <&clk_sys100m>;
power-domains = <&scmi_devpd IMX95_PD_HSIO_TOP>;
@@ -1844,7 +1844,7 @@ pcie0: pcie@...00000 {
<&scmi_clk IMX95_CLK_HSIOPLL>,
<&scmi_clk IMX95_CLK_HSIOPLL_VCO>,
<&scmi_clk IMX95_CLK_HSIOPCIEAUX>,
- <&hsio_blk_ctl 0>;
+ <&hsio_blk_ctl IMX95_CLK_HSIOMIX_PCIE_CLK_GATE>;
clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux", "ref";
assigned-clocks = <&scmi_clk IMX95_CLK_HSIOPLL_VCO>,
<&scmi_clk IMX95_CLK_HSIOPLL>,
@@ -1919,7 +1919,7 @@ pcie1: pcie@...80000 {
<&scmi_clk IMX95_CLK_HSIOPLL>,
<&scmi_clk IMX95_CLK_HSIOPLL_VCO>,
<&scmi_clk IMX95_CLK_HSIOPCIEAUX>,
- <&hsio_blk_ctl 0>;
+ <&hsio_blk_ctl IMX95_CLK_HSIOMIX_PCIE_CLK_GATE>;
clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux", "ref";
assigned-clocks = <&scmi_clk IMX95_CLK_HSIOPLL_VCO>,
<&scmi_clk IMX95_CLK_HSIOPLL>,
--
2.34.1
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