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Message-ID: <643a5776c383a501b129cd0f867395c0ccf80566.camel@linaro.org>
Date: Wed, 19 Nov 2025 11:16:46 +0000
From: André Draszik <andre.draszik@...aro.org>
To: Vinod Koul <vkoul@...nel.org>
Cc: Peter Griffin <peter.griffin@...aro.org>, Tudor Ambarus	
 <tudor.ambarus@...aro.org>, Will McVicker <willmcvicker@...gle.com>, 
	kernel-team@...roid.com, linux-phy@...ts.infradead.org, 
	linux-arm-kernel@...ts.infradead.org, linux-samsung-soc@...r.kernel.org, 
	linux-kernel@...r.kernel.org, stable@...r.kernel.org, Kishon Vijay Abraham
 I	 <kishon@...nel.org>, Krzysztof Kozlowski <krzk@...nel.org>, Alim Akhtar	
 <alim.akhtar@...sung.com>
Subject: Re: [PATCH] phy: exynos5-usbdrd: fix clock prepare imbalance

On Mon, 2025-10-06 at 09:07 +0100, André Draszik wrote:
> Commit f4fb9c4d7f94 ("phy: exynos5-usbdrd: allow DWC3 runtime suspend
> with UDC bound (E850+)") incorrectly added clk_bulk_disable() as the
> inverse of clk_bulk_prepare_enable() while it should have of course
> used clk_bulk_disable_unprepare(). This means incorrect reference
> counts to the CMU driver remain.
> 
> Update the code accordingly.
> 
> Fixes: f4fb9c4d7f94 ("phy: exynos5-usbdrd: allow DWC3 runtime suspend with UDC bound (E850+)")
> CC: stable@...r.kernel.org
> Signed-off-by: André Draszik <andre.draszik@...aro.org>

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