linux-kernel - Re: [PATCH 1/3] dt-bindings: usb: dwc3-xilinx: Add MMI USB support on Versal Gen2 platform

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Message-ID: <20251120-affable-markhor-of-authority-a9e63c@kuoka>
Date: Thu, 20 Nov 2025 09:17:49 +0100
From: Krzysztof Kozlowski <krzk@...nel.org>
To: Radhey Shyam Pandey <radhey.shyam.pandey@....com>
Cc: gregkh@...uxfoundation.org, robh@...nel.org, krzk+dt@...nel.org, 
	conor+dt@...nel.org, michal.simek@....com, Thinh.Nguyen@...opsys.com, 
	p.zabel@...gutronix.de, linux-usb@...r.kernel.org, devicetree@...r.kernel.org, 
	linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org, git@....com
Subject: Re: [PATCH 1/3] dt-bindings: usb: dwc3-xilinx: Add MMI USB support
 on Versal Gen2 platform

On Thu, Nov 20, 2025 at 01:00:34AM +0530, Radhey Shyam Pandey wrote:
> Versal Gen2 platform multimedia integrated (MMI) module has a USB3.2 Gen
> 2x1 Dual Role Device IP. Introduce a new compatibility string to support
> it and make reg optional as the register space for USB wrapper IP is moved
> to MMI System-Level Control registers.
> 
> Signed-off-by: Radhey Shyam Pandey <radhey.shyam.pandey@....com>
> ---
>  .../devicetree/bindings/usb/dwc3-xilinx.yaml  | 19 ++++++++++++++++---
>  1 file changed, 16 insertions(+), 3 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/usb/dwc3-xilinx.yaml b/Documentation/devicetree/bindings/usb/dwc3-xilinx.yaml
> index d6823ef5f9a7..502294649a6b 100644
> --- a/Documentation/devicetree/bindings/usb/dwc3-xilinx.yaml
> +++ b/Documentation/devicetree/bindings/usb/dwc3-xilinx.yaml
> @@ -15,6 +15,7 @@ properties:
>        - enum:
>            - xlnx,zynqmp-dwc3
>            - xlnx,versal-dwc3
> +          - xlnx,versal2-mmi-dwc3

All other cases were calling your SoC "versal2", not "versal2-mmi".

Add here missing blank line.

>    reg:
>      maxItems: 1
>  
> @@ -37,8 +38,9 @@ properties:
>        A list of phandle and clock-specifier pairs for the clocks
>        listed in clock-names.
>      items:
> -      - description: Master/Core clock, has to be >= 125 MHz
> -          for SS operation and >= 60MHz for HS operation.
> +      - description: Master/Core clock, has to be >= 156.25MHz in SSP
> +          mode, >= 125 MHz for SS operation and >= 60MHz for HS
> +          operation.
>        - description: Clock source to core during PHY power down.
>  
>    clock-names:
> @@ -87,7 +89,6 @@ patternProperties:
>  
>  required:
>    - compatible
> -  - reg

Hm? No. Block without address space makes little sense and is completely
different device.

Look at this binding - there is no way this device can be programmed
anywhow, because mentionned MMI sys registers are not there.

This is a messy, incomplete and confusing change. We ask always to post
complete bindings, for complete hardware, so put attention to this.

Best regards,
Krzysztof