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Message-ID: <CAMuHMdXireT6xVeWBd_OhbhOt8iJceuYCChM8Smd5+msZaxoRg@mail.gmail.com>
Date: Fri, 21 Nov 2025 15:30:11 +0100
From: Geert Uytterhoeven <geert@...ux-m68k.org>
To: Biju <biju.das.au@...il.com>
Cc: Greg Kroah-Hartman <gregkh@...uxfoundation.org>, Jiri Slaby <jirislaby@...nel.org>, 
	Biju Das <biju.das.jz@...renesas.com>, 
	Wolfram Sang <wsa+renesas@...g-engineering.com>, 
	Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>, 
	Claudiu Beznea <claudiu.beznea.uj@...renesas.com>, Nam Cao <namcao@...utronix.de>, 
	linux-kernel@...r.kernel.org, linux-serial@...r.kernel.org, 
	linux-renesas-soc@...r.kernel.org, stable@...nel.org
Subject: Re: [PATCH v3 2/2] serial: sh-sci: Fix deadlock during RSCI FIFO
 overrun error

On Fri, 14 Nov 2025 at 11:13, Biju <biju.das.au@...il.com> wrote:
> From: Biju Das <biju.das.jz@...renesas.com>
>
> On RSCI IP, a deadlock occurs during a FIFO overrun error, as it uses a
> different register to clear the FIFO overrun error status.
>
> Cc: stable@...nel.org
> Fixes: 0666e3fe95ab ("serial: sh-sci: Add support for RZ/T2H SCI")
> Signed-off-by: Biju Das <biju.das.jz@...renesas.com>
> ---
> v2->v3:
>  * Dropped overrun_clr from struct sci_port_params_bits
>  * All of the CFCLR_*C clearing bits match the corresponding
>    CSR_*status bits. So, reused the overrun mask for irq clearing.

Reviewed-by: Geert Uytterhoeven <geert+renesas@...der.be>

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@...ux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

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