Message-ID: <20251121160842.371922-1-biju.das.jz@bp.renesas.com>
Date: Fri, 21 Nov 2025 16:08:07 +0000
From: Biju <biju.das.au@...il.com>
To: Uwe Kleine-König <ukleinek@...nel.org>,
	Geert Uytterhoeven <geert+renesas@...der.be>,
	Linus Walleij <linus.walleij@...aro.org>,
	Philipp Zabel <p.zabel@...gutronix.de>,
	Magnus Damm <magnus.damm@...il.com>
Cc: Biju Das <biju.das.jz@...renesas.com>,
	linux-kernel@...r.kernel.org,
	linux-pwm@...r.kernel.org,
	linux-renesas-soc@...r.kernel.org,
	linux-gpio@...r.kernel.org,
	Prabhakar Mahadev Lad <prabhakar.mahadev-lad.rj@...renesas.com>,
	Biju Das <biju.das.au@...il.com>
Subject: [PATCH v8 00/15] Add RZ/G2L POEG support

From: Biju Das <biju.das.jz@...renesas.com>

The output pins of the general PWM timer (GPT) can be disabled by using
the port output enabling function for the GPT (POEG). Specifically, either
of the following ways can be used.

  * Input level detection of the GTETRGA to GTETRGD pins.
  * Output-disable request from the GPT.
  * Register setting(ie, by setting POEGGn.SSF to 1)

This patch series adds basic support for user control and output-disable
requests from the GTETRGn pins by using poeg char device.

Merged the pwm[2] and poeg[6] patch series together to get an overall view
of the system and also both are linked devices.

Patch #8 to patch #15 are just for testing Output-disable request from
the GPT

When dead time error occurs or the GTIOCA pin output value is the same as
the GTIOCB pin output value, output protection is required. GPT detects
this condition and generates output disable requests to POEG based on the
settings in the output disable request permission bits, such as
GTINTAD.GRP{DTE,ABH,ABL}. After the POEG receives output disable requests
from each channel and calculates external input using an OR operation, the
POEG disables the output of the GTIOCxA and GTIOCxB pins.

A sample test app is developed to handle POEG events. The POEG handles
output disable request from GPT and send an event to userspace. The
userspace with the help of poeg clears the fault condition.

This patch#2 on this series depend upon[1]
[1] https://lore.kernel.org/all/20251121133654.364688-1-biju.das.jz@bp.renesas.com/

Ref:
PWM:
[2] https://lore.kernel.org/all/20250226144531.176819-5-biju.das.jz@bp.renesas.com/
[3] https://lore.kernel.org/all/20240220194318.672443-5-biju.das.jz@bp.renesas.com/
[4] https://lore.kernel.org/all/20230228150756.482432-1-biju.das.jz@bp.renesas.com/
[5] https://lore.kernel.org/all/20221215205843.4074504-1-biju.das.jz@bp.renesas.com/
POEG:
[6] https://lore.kernel.org/all/20230328101011.185594-1-biju.das.jz@bp.renesas.com/

Merge strategy:
 patch #1-#2  PWM subsystem
 patch #3-#4  Pinctrl subsytem
 patch #5-#7  SoC

v7->v8:
 * Merged the pwm[2] and poeg[6] patches together to get an overall view
   of the system and also both are linked devices.
 * Add ack from Rob for the binding patch#3.
 * Replaced return type of rzg2l_gpt_poeg_init() from void->int and
   probe() checks this return value.
 * Added more error checks in rzg2l_gpt_poeg_init().
 * Replaced config name from POEG_RZG2L->RENESAS_RZG2L_POEG.
 * Updated POEG Kconfig dependency with PWM
 * Dropped static variable minor_n and instead using the value of
   "renesas,poeg-id".
 * Replaced devm_reset_*_exclusive()->devm_reset_*_exclusive_deasserted()
 * Replaced pm_runtime_enable() with devm variant.
 * Added support for handling output-disable requests from the GTETRGn
   pins.
 * Replaced the macros RZG2L_POEG_USR_CTRL_{EN,DiS}ABLE_CMD to 
   RZG2L_POEG_OUTPUT_DISABLE_USR_{EN,DIS}ABLE_CMD.
 * Replaced '&pdev->dev' by 'dev' in probe().
 * Added DT and config patch
v6->v7:
 * Documented renesas,poeg-config optional property for configuring the
   system for pin output disable.
 * Used DT to handle the system configuration
 * Added poeg char device for user control support to enable/disable
   output from GPT
 * Replaced iowrite32/ioread32-> writel/readl
 * Dropped of_match_ptr from .of_match_table
v5->v6:
 * Dropped binding patch as it is accepted for 6.4.
 * Added sysfs support for configuring pin output disable 
   function in a generic way.
v4->v5:
 * Added Rb tag from Rob.
 * Updated kernel version in sysfs doc.
v3->v4:
 * Replaced companion->renesas,gpt for the phandle to gpt instance
 * Replaced renesas,id->renesas,poeg-id
 * Removed default from renesas,poeg-id as default for a required
   property doesn't make much sense.
 * Updated the example and required properties with above changes
v2->v3:
 * Removed Rb tag from Rob as there are some changes introduced.
 * Added companion property, so that poeg can link with gpt device
 * Documented renesas,id, as identifier for POEGG{A,B,C,D}.
 * Updated the binding example.
 * Added sysfs documentation for output_disable
 * PWM_RZG2L_GPT implies ARCH_RZG2L. So removed ARCH_RZG2L dependency
 * Used dev_get_drvdata to get device data
 * Replaced sprintf->sysfs_emit in show().
v1->v2:
 * Updated binding description.
 * Renamed the file poeg-rzg2l->rzg2l-poeg
 * Removed the macro POEGG as there is only single register and
   updated rzg2l_poeg_write() and rzg2l_poeg_read()
 * Updated error handling in probe()
REF->v1:
 * Modelled as pincontrol as most of its configuration is intended to be
   static and moved driver files from soc to pincontrol directory.
 * Updated reg size in dt binding example.
 * Updated Kconfig

logs:
With renesas,poeg-config = <1>;
root@...rc-rzv2l:~# /poeg.sh
Test case 1 user POEG control
Read at address  0x10048434 (0xffffbdcc4434): 0x031B031B
Read at address  0x10048438 (0xffff9341f438): 0x03000000
Read at address  0x10049400 (0xffffacdfe400): 0x00000000
[POEG]open
[POEG] user control pin output disable disabled
[POEG]close
[POEG]open
[POEG] user control pin output disable enabled
[POEG]close
Read at address  0x10048434 (0xffff89990434): 0x031B031B
Read at address  0x10048438 (0xffffb5b98438): 0x03000000
Read at address  0x10049400 (0xffff949ef400): 0x00000008
[POEG]open
[POEG] user control pin output disable disabled
[POEG]close
 74:          0          0    GICv3 357 Level     10049400.poeg
Read at address  0x10048434 (0xffff8f401434): 0x031B031B
Read at address  0x10048438 (0xffffbb55b438): 0x03000000
Read at address  0x10049400 (0xffff969c4400): 0x00000000

With renesas,poeg-config = <2>;
root@...rc-rzv2l:~# /poeg.sh
Test case 2  GPT control
Read at address  0x10048434 (0xffffa2e9c434): 0x031B031B
[POEG]open
[POEG] GPT control configure IRQ
Read at address  0x10048438 (0xffff88063438): 0x23000000
Read at address  0x10049400 (0xffff9a09a400): 0x00000020
gpt ch:4, irq=2
gpt ch:4, irq=2
gpt ch:4, irq=2
gpt ch:4, irq=2
Read at address  0x10048434 (0xffff90768434): 0x021B031B
Read at address  0x10048438 (0xffffa652c438): 0x23000000
Read at address  0x10049400 (0xffffa2b64400): 0x00000020
 74:          5          0    GICv3 357 Level     10049400.poeg

With renesas,poeg-config = <4>;
root@...rc-rzv2l:~# /poeg.sh
Test case 2  GPT control
Read at address  0x10048434 (0xffff81226434): 0x031B031B
[POEG]open
[POEG] GPT control configure IRQ
Read at address  0x10048438 (0xffffa35fd438): 0x43000000
Read at address  0x10049400 (0xffffb4a0e400): 0x00000020
gpt ch:4, irq=4
gpt ch:4, irq=4
gpt ch:4, irq=4
gpt ch:4, irq=4
Read at address  0x10048434 (0xffff81df7434): 0x021B031B
Read at address  0x10048438 (0xffffa8fdf438): 0x43000000
Read at address  0x10049400 (0xffff9f49b400): 0x00000020
 74:          5          0    GICv3 357 Level     10049400.poeg

Biju Das (15):
  dt-bindings: pwm: rzg2l-gpt: Document renesas,poegs property
  pwm: rzg2l-gpt: Add support for gpt linking with poeg
  dt-bindings: pinctrl: rzg2l-poeg: Document renesas,poeg-config
    property
  drivers: pinctrl: renesas: Add RZ/G2L POEG driver support
  arm64: dts: renesas: r9a07g0{4,5}4: Add POEG nodes
  arm64: dts: renesas: rzg2l-smarc: Enable POEGG{A,B,C,D} on carrier
    board
  arm64: defconfig: Enable Renesas RZ/G2L POEG interface
  tools/poeg: Add test app for poeg
  pwm: rzg2l-gpt: Add support for output disable request from gpt
  pwm: rzg2l-gpt: Add support for output disable when both output low
  pwm: rzg2l-gpt: Add support for output disable on dead time error
  pinctrl: renesas: rzg2l-poeg: Add support for GPT Output-Disable
    Request
  pinctrl: renesas: rzg2l-poeg: output-disable request from GPT when
    both outputs are low.
  pinctrl: renesas: rzg2l-poeg: output-disable request from GPT on dead
    time error
  tools: poeg: Add support for handling GPT output request disable

 .../bindings/pinctrl/renesas,rzg2l-poeg.yaml  |  16 +
 .../bindings/pwm/renesas,rzg2l-gpt.yaml       |  23 +
 arch/arm64/boot/dts/renesas/r9a07g044.dtsi    |  52 ++
 arch/arm64/boot/dts/renesas/r9a07g054.dtsi    |  52 ++
 arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi  |   6 +
 arch/arm64/configs/defconfig                  |   1 +
 drivers/pinctrl/renesas/Kconfig               |   2 +
 drivers/pinctrl/renesas/Makefile              |   2 +
 drivers/pinctrl/renesas/poeg/Kconfig          |  11 +
 drivers/pinctrl/renesas/poeg/Makefile         |   2 +
 drivers/pinctrl/renesas/poeg/rzg2l-poeg.c     | 481 ++++++++++++++++++
 drivers/pwm/pwm-rzg2l-gpt.c                   | 212 ++++++++
 include/linux/pinctrl/rzg2l-poeg.h            |  26 +
 include/linux/pwm/rzg2l-gpt.h                 |  44 ++
 tools/poeg/Build                              |   1 +
 tools/poeg/Makefile                           |  53 ++
 tools/poeg/poeg_app.c                         |  95 ++++
 17 files changed, 1079 insertions(+)
 create mode 100644 drivers/pinctrl/renesas/poeg/Kconfig
 create mode 100644 drivers/pinctrl/renesas/poeg/Makefile
 create mode 100644 drivers/pinctrl/renesas/poeg/rzg2l-poeg.c
 create mode 100644 include/linux/pinctrl/rzg2l-poeg.h
 create mode 100644 include/linux/pwm/rzg2l-gpt.h
 create mode 100644 tools/poeg/Build
 create mode 100644 tools/poeg/Makefile
 create mode 100644 tools/poeg/poeg_app.c

-- 
2.43.0

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