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Message-ID: <20251121233545.GJ233636@ziepe.ca>
Date: Fri, 21 Nov 2025 19:35:45 -0400
From: Jason Gunthorpe <jgg@...pe.ca>
To: Sairaj Kodilkar <sarunkod@....com>
Cc: joro@...tes.org, suravee.suthikulpanit@....com, will@...nel.org,
robin.murphy@....com, kevin.tian@...el.com, iommu@...ts.linux.dev,
linux-kernel@...r.kernel.org, vasant.hegde@....com
Subject: Re: [RFC PATCH] iommu/amd: Add control register in `struct
iommu_hw_info_amd`
On Wed, Oct 29, 2025 at 03:28:46PM +0530, Sairaj Kodilkar wrote:
> When user does IOMMU_GET_HW_INFO ioctl, read the IOMMU control
> register (MMIO offset 0x0018) and return it as part of
> `struct iommu_hw_info_amd`.
>
> Userspace can use this information to determine the features
> supported by the underlying host kernel.
>
> Signed-off-by: Sairaj Kodilkar <sarunkod@....com>
> ---
>
> The patch exposes the control register to the user space so that QEMU
> can determine the list of features enabled by the host IOMMU driver
> when there are passthrough devices. QEMU can use this information to
> selectively enable the guest feature. One example of such feature is
> enabling upto 2048 MSIs for passthrough devices. QEMU must not enable
> this feature for passthrough devices when host IOMMU driver has not
> enabled it.
Please document in the uapi header what bits are meaningful and
userspace can safely access..
You are OK that a 0 register means the kernel is old?
Jason
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