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Message-ID:
 <TY3PR01MB11346B5AAC1CBB54361ABAE5286D2A@TY3PR01MB11346.jpnprd01.prod.outlook.com>
Date: Sat, 22 Nov 2025 12:30:30 +0000
From: Biju Das <biju.das.jz@...renesas.com>
To: geert <geert@...ux-m68k.org>, biju.das.au <biju.das.au@...il.com>
CC: Greg Kroah-Hartman <gregkh@...uxfoundation.org>, Jiri Slaby
	<jirislaby@...nel.org>, Rob Herring <robh@...nel.org>, Krzysztof Kozlowski
	<krzk+dt@...nel.org>, Conor Dooley <conor+dt@...nel.org>, magnus.damm
	<magnus.damm@...il.com>, wsa+renesas <wsa+renesas@...g-engineering.com>,
	Prabhakar Mahadev Lad <prabhakar.mahadev-lad.rj@...renesas.com>,
	"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
	"linux-serial@...r.kernel.org" <linux-serial@...r.kernel.org>,
	"devicetree@...r.kernel.org" <devicetree@...r.kernel.org>,
	"linux-renesas-soc@...r.kernel.org" <linux-renesas-soc@...r.kernel.org>
Subject: RE: [PATCH v3 12/13] serial: sh-sci: Add support for RZ/G3E RSCI SCIF

Hi Geert,

Thanks for the feedback.

> -----Original Message-----
> From: Geert Uytterhoeven <geert@...ux-m68k.org>
> Sent: 21 November 2025 14:46
> Subject: Re: [PATCH v3 12/13] serial: sh-sci: Add support for RZ/G3E RSCI SCIF
> 
> Hi Biju,
> 
> On Fri, 14 Nov 2025 at 11:52, Biju <biju.das.au@...il.com> wrote:
> > From: Biju Das <biju.das.jz@...renesas.com>
> >
> > Add support for RZ/G3E RSCI SCIF(a.k.a FIFO mode). RSCI IP found on
> > the RZ/G3E SoC is similar to RZ/T2H, but it has a 32-stage FIFO. it
> > has 6
> > clocks(5 module clocks + 1 external clock) instead of 3 clocks(2
> > module clocks + 1 external clock) on T2H and has multiple resets. Add
> > support for the hardware flow control.
> >
> > Signed-off-by: Biju Das <biju.das.jz@...renesas.com>
> > ---
> > v2->v3:
> >  * Dropped cpu_relax() from rsci_finish_console_write() and added a
> >    comment.
> >  * Added sci_is_rsci_fifo_type() helper for reuse in probe() and remove().
> 
> Thanks for the update!
> 
> > --- a/drivers/tty/serial/sh-sci.c
> > +++ b/drivers/tty/serial/sh-sci.c
> > @@ -3563,6 +3563,11 @@ static struct uart_driver sci_uart_driver = {
> >         .cons           = SCI_CONSOLE,
> >  };
> >
> > +static bool sci_is_rsci_fifo_type(u8 type) {
> > +       return (type == SCI_PORT_RSCI || type == RSCI_PORT_SCIF); }
> > +
> >  static void sci_remove(struct platform_device *dev)  {
> >         struct sci_port *s = platform_get_drvdata(dev); @@ -3574,7
> > +3579,7 @@ static void sci_remove(struct platform_device *dev)
> >         if (s->port.fifosize > 1)
> >                 device_remove_file(&dev->dev, &dev_attr_rx_fifo_trigger);
> >         if (type == PORT_SCIFA || type == PORT_SCIFB || type == PORT_HSCIF ||
> > -           type == SCI_PORT_RSCI)
> > +           sci_is_rsci_fifo_type(type))
> 
> I think Jiri intended[1] having a helper that covers all cases, not
> just the two RSCI variants. E.g. sci_has_fifo(u8 type).

OK, I will update to cover all the variants.

Cheers,
Biju

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