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Message-ID: <20251124065457.3630949-3-qiuxu.zhuo@intel.com>
Date: Mon, 24 Nov 2025 14:54:57 +0800
From: Qiuxu Zhuo <qiuxu.zhuo@...el.com>
To: Tony Luck <tony.luck@...el.com>,
Borislav Petkov <bp@...en8.de>
Cc: Qiuxu Zhuo <qiuxu.zhuo@...el.com>,
Jianfeng Gao <jianfeng.gao@...el.com>,
Yi Lai <yi1.lai@...el.com>,
linux-edac@...r.kernel.org,
linux-kernel@...r.kernel.org
Subject: [PATCH 2/2] EDAC/igen6: Make masks of {MCHBAR, TOM, TOUUD, ECC_ERROR_LOG} configurable
The masks used to retrieve base addresses from {MCHBAR, TOM, TOUUD,
ECC_ERROR_LOG} registers can be CPU model-specific. Currently,
igen6_edac hard-codes these masks with the most significant bit at
38, while some CPUs have extended the most significant bit to bit 41
or bit 45.
Systems with more than 512GB (2^39) memory need this extension to get
correct masks. But all CPUs currently supported by igen6_edac support
max memory less than 512GB (e.g., max memory size for Raptor Lake
systems is 192GB, for Alder Lake systems is 128GB, ...), which means
the previous hard-coded most significant bit 38 still works properly.
So backporting this patch to stable kernels is not necessary.
To make these masks reflect the CPUs' real support and easily support
future Intel client CPUs supported by igen6_edac that have more than
512GB memory, add four new fields to structure res_config to make these
masks CPU model-specific and configure them properly.
Tested-by: Jianfeng Gao <jianfeng.gao@...el.com>
Signed-off-by: Qiuxu Zhuo <qiuxu.zhuo@...el.com>
---
drivers/edac/igen6_edac.c | 67 ++++++++++++++++++++++++++++++++-------
1 file changed, 55 insertions(+), 12 deletions(-)
diff --git a/drivers/edac/igen6_edac.c b/drivers/edac/igen6_edac.c
index 5d887a3115f0..db4aa9f581e3 100644
--- a/drivers/edac/igen6_edac.c
+++ b/drivers/edac/igen6_edac.c
@@ -79,15 +79,11 @@
#define ECC_ERROR_LOG_OFFSET (IBECC_BASE + res_cfg->ibecc_error_log_offset)
#define ECC_ERROR_LOG_CE BIT_ULL(62)
#define ECC_ERROR_LOG_UE BIT_ULL(63)
-#define ECC_ERROR_LOG_ADDR_SHIFT 5
-#define ECC_ERROR_LOG_ADDR(v) GET_BITFIELD(v, 5, 38)
-#define ECC_ERROR_LOG_ADDR45(v) GET_BITFIELD(v, 5, 45)
#define ECC_ERROR_LOG_SYND(v) GET_BITFIELD(v, 46, 61)
/* Host MMIO base address */
#define MCHBAR_OFFSET 0x48
#define MCHBAR_EN BIT_ULL(0)
-#define MCHBAR_BASE(v) (GET_BITFIELD(v, 16, 38) << 16)
#define MCHBAR_SIZE 0x10000
/* Parameters for the channel decode stage */
@@ -125,10 +121,21 @@
#define MEM_SLICE_HASH_MASK(v) (GET_BITFIELD(v, 6, 19) << 6)
#define MEM_SLICE_HASH_LSB_MASK_BIT(v) GET_BITFIELD(v, 24, 26)
+/* Non-constant mask variant of FIELD_GET() */
+#define field_get(mask, reg) (((reg) & (mask)) >> (ffs(mask) - 1))
+
static struct res_config {
bool machine_check;
/* The number of present memory controllers. */
int num_imc;
+ /* Host MMIO configuration */
+ u64 reg_mchbar_mask;
+ /* Top of memory */
+ u64 reg_tom_mask;
+ /* Top of upper usable DRAM */
+ u64 reg_touud_mask;
+ /* IBECC error log */
+ u64 reg_eccerrlog_addr_mask;
u32 imc_base;
u32 cmf_base;
u32 cmf_size;
@@ -305,7 +312,8 @@ static int get_mchbar(struct pci_dev *pdev, u64 *mchbar)
return -ENODEV;
}
- *mchbar = MCHBAR_BASE(u.v);
+ *mchbar = u.v & res_cfg->reg_mchbar_mask;
+ edac_dbg(2, "MCHBAR 0x%llx (reg 0x%llx)\n", *mchbar, u.v);
return 0;
}
@@ -481,11 +489,15 @@ static u64 adl_err_addr_to_imc_addr(u64 eaddr, int mc)
static u64 rpl_p_err_addr(u64 ecclog)
{
- return ECC_ERROR_LOG_ADDR45(ecclog);
+ return field_get(res_cfg->reg_eccerrlog_addr_mask, ecclog);
}
static struct res_config ehl_cfg = {
.num_imc = 1,
+ .reg_mchbar_mask = GENMASK_ULL(38, 16),
+ .reg_tom_mask = GENMASK_ULL(38, 20),
+ .reg_touud_mask = GENMASK_ULL(38, 20),
+ .reg_eccerrlog_addr_mask = GENMASK_ULL(38, 5),
.imc_base = 0x5000,
.ibecc_base = 0xdc00,
.ibecc_available = ehl_ibecc_available,
@@ -496,6 +508,10 @@ static struct res_config ehl_cfg = {
static struct res_config icl_cfg = {
.num_imc = 1,
+ .reg_mchbar_mask = GENMASK_ULL(38, 16),
+ .reg_tom_mask = GENMASK_ULL(38, 20),
+ .reg_touud_mask = GENMASK_ULL(38, 20),
+ .reg_eccerrlog_addr_mask = GENMASK_ULL(38, 5),
.imc_base = 0x5000,
.ibecc_base = 0xd800,
.ibecc_error_log_offset = 0x170,
@@ -507,6 +523,10 @@ static struct res_config icl_cfg = {
static struct res_config tgl_cfg = {
.machine_check = true,
.num_imc = 2,
+ .reg_mchbar_mask = GENMASK_ULL(38, 17),
+ .reg_tom_mask = GENMASK_ULL(38, 20),
+ .reg_touud_mask = GENMASK_ULL(38, 20),
+ .reg_eccerrlog_addr_mask = GENMASK_ULL(38, 5),
.imc_base = 0x5000,
.cmf_base = 0x11000,
.cmf_size = 0x800,
@@ -521,6 +541,10 @@ static struct res_config tgl_cfg = {
static struct res_config adl_cfg = {
.machine_check = true,
.num_imc = 2,
+ .reg_mchbar_mask = GENMASK_ULL(41, 17),
+ .reg_tom_mask = GENMASK_ULL(41, 20),
+ .reg_touud_mask = GENMASK_ULL(41, 20),
+ .reg_eccerrlog_addr_mask = GENMASK_ULL(45, 5),
.imc_base = 0xd800,
.ibecc_base = 0xd400,
.ibecc_error_log_offset = 0x68,
@@ -532,6 +556,10 @@ static struct res_config adl_cfg = {
static struct res_config adl_n_cfg = {
.machine_check = true,
.num_imc = 1,
+ .reg_mchbar_mask = GENMASK_ULL(41, 17),
+ .reg_tom_mask = GENMASK_ULL(41, 20),
+ .reg_touud_mask = GENMASK_ULL(41, 20),
+ .reg_eccerrlog_addr_mask = GENMASK_ULL(45, 5),
.imc_base = 0xd800,
.ibecc_base = 0xd400,
.ibecc_error_log_offset = 0x68,
@@ -543,6 +571,10 @@ static struct res_config adl_n_cfg = {
static struct res_config rpl_p_cfg = {
.machine_check = true,
.num_imc = 2,
+ .reg_mchbar_mask = GENMASK_ULL(41, 17),
+ .reg_tom_mask = GENMASK_ULL(41, 20),
+ .reg_touud_mask = GENMASK_ULL(41, 20),
+ .reg_eccerrlog_addr_mask = GENMASK_ULL(45, 5),
.imc_base = 0xd800,
.ibecc_base = 0xd400,
.ibecc_error_log_offset = 0x68,
@@ -555,6 +587,10 @@ static struct res_config rpl_p_cfg = {
static struct res_config mtl_ps_cfg = {
.machine_check = true,
.num_imc = 2,
+ .reg_mchbar_mask = GENMASK_ULL(41, 17),
+ .reg_tom_mask = GENMASK_ULL(41, 20),
+ .reg_touud_mask = GENMASK_ULL(41, 20),
+ .reg_eccerrlog_addr_mask = GENMASK_ULL(38, 5),
.imc_base = 0xd800,
.ibecc_base = 0xd400,
.ibecc_error_log_offset = 0x170,
@@ -566,6 +602,10 @@ static struct res_config mtl_ps_cfg = {
static struct res_config mtl_p_cfg = {
.machine_check = true,
.num_imc = 2,
+ .reg_mchbar_mask = GENMASK_ULL(41, 17),
+ .reg_tom_mask = GENMASK_ULL(41, 20),
+ .reg_touud_mask = GENMASK_ULL(41, 20),
+ .reg_eccerrlog_addr_mask = GENMASK_ULL(38, 5),
.imc_base = 0xd800,
.ibecc_base = 0xd400,
.ibecc_error_log_offset = 0x170,
@@ -577,6 +617,10 @@ static struct res_config mtl_p_cfg = {
static struct res_config wcl_cfg = {
.machine_check = true,
.num_imc = 1,
+ .reg_mchbar_mask = GENMASK_ULL(41, 17),
+ .reg_tom_mask = GENMASK_ULL(41, 20),
+ .reg_touud_mask = GENMASK_ULL(41, 20),
+ .reg_eccerrlog_addr_mask = GENMASK_ULL(38, 5),
.imc_base = 0xd800,
.ibecc_base = 0xd400,
.ibecc_error_log_offset = 0x170,
@@ -908,8 +952,8 @@ static void ecclog_work_cb(struct work_struct *work)
if (res_cfg->err_addr)
eaddr = res_cfg->err_addr(node->ecclog);
else
- eaddr = ECC_ERROR_LOG_ADDR(node->ecclog) <<
- ECC_ERROR_LOG_ADDR_SHIFT;
+ eaddr = node->ecclog & res_cfg->reg_eccerrlog_addr_mask;
+
res.mc = node->mc;
res.sys_addr = res_cfg->err_addr_to_sys_addr(eaddr, res.mc);
res.imc_addr = res_cfg->err_addr_to_imc_addr(eaddr, res.mc);
@@ -1129,8 +1173,7 @@ static int debugfs_u64_set(void *data, u64 val)
pr_warn_once("Fake error to 0x%llx injected via debugfs\n", val);
- val >>= ECC_ERROR_LOG_ADDR_SHIFT;
- ecclog = (val << ECC_ERROR_LOG_ADDR_SHIFT) | ECC_ERROR_LOG_CE;
+ ecclog = (val & res_cfg->reg_eccerrlog_addr_mask) | ECC_ERROR_LOG_CE;
if (!ecclog_gen_pool_add(0, ecclog))
irq_work_queue(&ecclog_irq_work);
@@ -1196,7 +1239,7 @@ static int igen6_pci_setup(struct pci_dev *pdev, u64 *mchbar)
goto fail;
}
- igen6_tom = u.v & GENMASK_ULL(38, 20);
+ igen6_tom = u.v & res_cfg->reg_tom_mask;
if (get_mchbar(pdev, mchbar))
goto fail;
@@ -1207,7 +1250,7 @@ static int igen6_pci_setup(struct pci_dev *pdev, u64 *mchbar)
else if (pci_read_config_dword(pdev, TOUUD_OFFSET + 4, &u.v_hi))
edac_dbg(2, "Failed to read upper TOUUD\n");
else
- igen6_touud = u.v & GENMASK_ULL(38, 20);
+ igen6_touud = u.v & res_cfg->reg_touud_mask;
#endif
return 0;
--
2.43.0
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