linux-kernel - Re: [PATCH v3 net-next 3/3] net: enetc: update the base address of port MDIO registers for ENETC v4

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Message-ID: <c177a361-84dc-4523-8b1f-5c6a4437b064@lunn.ch>
Date: Tue, 25 Nov 2025 17:19:58 +0100
From: Andrew Lunn <andrew@...n.ch>
To: Paolo Abeni <pabeni@...hat.com>
Cc: Wei Fang <wei.fang@....com>, claudiu.manoil@....com,
	vladimir.oltean@....com, xiaoning.wang@....com,
	andrew+netdev@...n.ch, davem@...emloft.net, edumazet@...gle.com,
	kuba@...nel.org, aziz.sellami@....com, imx@...ts.linux.dev,
	netdev@...r.kernel.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH v3 net-next 3/3] net: enetc: update the base address of
 port MDIO registers for ENETC v4

On Tue, Nov 25, 2025 at 11:05:06AM +0100, Paolo Abeni wrote:
> On 11/19/25 11:25 AM, Wei Fang wrote:
> > Each ENETC has a set of external MDIO registers to access its external
> > PHY based on its port EMDIO bus, these registers are used for MDIO bus
> > access, such as setting the PHY address, PHY register address and value,
> > read or write operations, C22 or C45 format, etc. The base address of
> > this set of registers has been modified in ENETC v4 and is different
> > from that in ENETC v1. So the base address needs to be updated so that
> > ENETC v4 can use port MDIO to manage its own external PHY.
> > 
> > Additionally, if ENETC has the PCS layer, it also has a set of internal
> > MDIO registers for managing its on-die PHY (PCS/Serdes). The base address
> > of this set of registers is also different from that of ENETC v1, so the
> > base address also needs to be updated so that ENETC v4 can support the
> > management of on-die PHY through the internal MDIO bus.
> > 
> > Signed-off-by: Wei Fang <wei.fang@....com>
> 
> Andrew, it's not clear to me if you are with the current patch version,
> could you please chime-in?

I say merge it. I'm not sure it is the best of architectures, but i
don't have time to dig into all the details in order to suggest
something better.

	Andrew