linux-kernel - Re: [PATCH v2] mmc: sdhci-of-dwcmshc: Promote the th1520 reset handling to ip level

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Message-ID: <CAPDyKFpu1Ag+dL6WqZPpE5B9kDBgo3VrpP7O64dqkgtqimUHdA@mail.gmail.com>
Date: Tue, 25 Nov 2025 14:00:23 +0100
From: Ulf Hansson <ulf.hansson@...aro.org>
To: Jisheng Zhang <jszhang@...nel.org>
Cc: Adrian Hunter <adrian.hunter@...el.com>, linux-mmc@...r.kernel.org, 
	linux-kernel@...r.kernel.org, shawn.lin@...k-chips.com
Subject: Re: [PATCH v2] mmc: sdhci-of-dwcmshc: Promote the th1520 reset
 handling to ip level

On Mon, 17 Nov 2025 at 01:19, Jisheng Zhang <jszhang@...nel.org> wrote:
>
> Commit 27e8fe0da3b7 ("mmc: sdhci-of-dwcmshc: Prevent stale command
> interrupt handling") clears pending interrupts when resetting
> host->pending_reset to ensure no pending stale interrupts after
> sdhci_threaded_irq restores interrupts. But this fix is only added for
> th1520 platforms, in fact per my test, this issue exists on all
> dwcmshc users, such as cv1800b, sg2002, and synaptics platforms.
>
> So promote the above reset handling from th1520 to ip level. And keep
> reset handling on rk, sg2042 and bf3 as is, until it's confirmed that
> the same issue exists on these platforms too.
>
> Fixes: 017199c2849c ("mmc: sdhci-of-dwcmshc: Add support for Sophgo CV1800B and SG2002")
> Signed-off-by: Jisheng Zhang <jszhang@...nel.org>

Applied for fixes and by adding a stable tag, thanks!

Kind regards
Uffe


> ---
> since v1:
>  - limit the promotion to only cv1800b, sg2002 and generic dwcmshc
>
>  drivers/mmc/host/sdhci-of-dwcmshc.c | 29 +++++++++++++++++------------
>  1 file changed, 17 insertions(+), 12 deletions(-)
>
> diff --git a/drivers/mmc/host/sdhci-of-dwcmshc.c b/drivers/mmc/host/sdhci-of-dwcmshc.c
> index eebd45389956..07e5df0f8beb 100644
> --- a/drivers/mmc/host/sdhci-of-dwcmshc.c
> +++ b/drivers/mmc/host/sdhci-of-dwcmshc.c
> @@ -289,6 +289,19 @@ static void dwcmshc_adma_write_desc(struct sdhci_host *host, void **desc,
>         sdhci_adma_write_desc(host, desc, addr, len, cmd);
>  }
>
> +static void dwcmshc_reset(struct sdhci_host *host, u8 mask)
> +{
> +       sdhci_reset(host, mask);
> +
> +       /* The dwcmshc does not comply with the SDHCI specification
> +        * regarding the "Software Reset for CMD line should clear 'Command
> +        * Complete' in the Normal Interrupt Status Register." Clear the bit
> +        * here to compensate for this quirk.
> +        */
> +       if (mask & SDHCI_RESET_CMD)
> +               sdhci_writel(host, SDHCI_INT_RESPONSE, SDHCI_INT_STATUS);
> +}
> +
>  static unsigned int dwcmshc_get_max_clock(struct sdhci_host *host)
>  {
>         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
> @@ -832,15 +845,7 @@ static void th1520_sdhci_reset(struct sdhci_host *host, u8 mask)
>         struct dwcmshc_priv *priv = sdhci_pltfm_priv(pltfm_host);
>         u16 ctrl_2;
>
> -       sdhci_reset(host, mask);
> -
> -       /* The T-Head 1520 SoC does not comply with the SDHCI specification
> -        * regarding the "Software Reset for CMD line should clear 'Command
> -        * Complete' in the Normal Interrupt Status Register." Clear the bit
> -        * here to compensate for this quirk.
> -        */
> -       if (mask & SDHCI_RESET_CMD)
> -               sdhci_writel(host, SDHCI_INT_RESPONSE, SDHCI_INT_STATUS);
> +       dwcmshc_reset(host, mask);
>
>         if (priv->flags & FLAG_IO_FIXED_1V8) {
>                 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
> @@ -886,7 +891,7 @@ static void cv18xx_sdhci_reset(struct sdhci_host *host, u8 mask)
>         struct dwcmshc_priv *priv = sdhci_pltfm_priv(pltfm_host);
>         u32 val, emmc_caps = MMC_CAP2_NO_SD | MMC_CAP2_NO_SDIO;
>
> -       sdhci_reset(host, mask);
> +       dwcmshc_reset(host, mask);
>
>         if ((host->mmc->caps2 & emmc_caps) == emmc_caps) {
>                 val = sdhci_readl(host, priv->vendor_specific_area1 + CV18XX_SDHCI_MSHC_CTRL);
> @@ -958,7 +963,7 @@ static void cv18xx_sdhci_post_tuning(struct sdhci_host *host)
>         val |= SDHCI_INT_DATA_AVAIL;
>         sdhci_writel(host, val, SDHCI_INT_STATUS);
>
> -       sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
> +       dwcmshc_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
>  }
>
>  static int cv18xx_sdhci_execute_tuning(struct sdhci_host *host, u32 opcode)
> @@ -1100,7 +1105,7 @@ static const struct sdhci_ops sdhci_dwcmshc_ops = {
>         .set_bus_width          = sdhci_set_bus_width,
>         .set_uhs_signaling      = dwcmshc_set_uhs_signaling,
>         .get_max_clock          = dwcmshc_get_max_clock,
> -       .reset                  = sdhci_reset,
> +       .reset                  = dwcmshc_reset,
>         .adma_write_desc        = dwcmshc_adma_write_desc,
>         .irq                    = dwcmshc_cqe_irq_handler,
>  };
> --
> 2.51.0
>