linux-kernel - Re: [PATCH] dt-bindings: spi: renesas,rzv2h-rspi: Document RZ/V2N SoC support

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Message-ID: <CAMuHMdUM8hN0xM2Q-Y_oGb+u=+ONabO-M-Wg+_5A-SStHm4pdw@mail.gmail.com>
Date: Wed, 26 Nov 2025 13:31:10 +0100
From: Geert Uytterhoeven <geert@...ux-m68k.org>
To: "Lad, Prabhakar" <prabhakar.csengg@...il.com>
Cc: Fabrizio Castro <fabrizio.castro.jz@...esas.com>, Mark Brown <broonie@...nel.org>, 
	Rob Herring <robh@...nel.org>, Krzysztof Kozlowski <krzk+dt@...nel.org>, Conor Dooley <conor+dt@...nel.org>, 
	Magnus Damm <magnus.damm@...il.com>, linux-spi@...r.kernel.org, 
	linux-renesas-soc@...r.kernel.org, devicetree@...r.kernel.org, 
	linux-kernel@...r.kernel.org, Biju Das <biju.das.jz@...renesas.com>, 
	Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
Subject: Re: [PATCH] dt-bindings: spi: renesas,rzv2h-rspi: Document RZ/V2N SoC support

Hi Prabhakar,

On Wed, 26 Nov 2025 at 13:11, Lad, Prabhakar <prabhakar.csengg@...il.com> wrote:
> On Wed, Nov 26, 2025 at 11:38 AM Geert Uytterhoeven
> > On Tue, 25 Nov 2025 at 22:45, Prabhakar <prabhakar.csengg@...il.com> wrote:
> > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
> > >
> > > Document the RSPI controller on the Renesas RZ/V2N SoC. The block is
> > > compatible with the RSPI implementation found on the RZ/V2H(P) family.
> > >
> > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
> >
> > > --- a/Documentation/devicetree/bindings/spi/renesas,rzv2h-rspi.yaml
> > > +++ b/Documentation/devicetree/bindings/spi/renesas,rzv2h-rspi.yaml
> > > @@ -12,6 +12,9 @@ maintainers:
> > >  properties:
> > >    compatible:
> > >      oneOf:
> > > +      - items:
> > > +          - const: renesas,r9a09g056-rspi # RZ/V2N
> > > +          - const: renesas,r9a09g057-rspi
> >
> > I am a bit intrigued too read that the initial value of the SPI
> > Transfer FIFO Status Register indicates 4 empty stages on RZ/V2H,
> > and 16 on RZ/V2N, while both variants have a 16-stage FIFO...
> >
> Both SoC variants report a value of 0x10 for the RSPIm_SPTFSR register.
>
> Rev.1.20 for RZ/V2N mentions, 16-stage
> Rev.1.30 for RZ/V2H mentions, 16-stage

My RZ/V2H Rev.1.20 says 4h (Section 7.5.2.2.19 SPI Transfer FIFO
Status Register (RSPIm_SPTFSR) and Table 7.5.2.1 List of Registers)

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@...ux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds