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Message-ID: <0b77ac0f-a18f-e577-ff92-98ddd1d2bed8@kernel.org>
Date: Wed, 26 Nov 2025 17:49:43 -0700 (MST)
From: Paul Walmsley <pjw@...nel.org>
To: Himanshu Chauhan <hchauhan@...tanamicro.com>
cc: paul.walmsley@...ive.com, palmer@...belt.com, aou@...s.berkeley.edu,
linux-riscv@...ts.infradead.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH v1 2/2] riscv: Introduce support for hardware
break/watchpoints
On Thu, 10 Jul 2025, Himanshu Chauhan wrote:
> RISC-V hardware breakpoint framework is built on top of perf subsystem
> and uses SBI debug trigger extension to
> install/uninstall/update/enable/disable hardware triggers as specified
> in Sdtrig ISA extension.
>
> Signed-off-by: Himanshu Chauhan <hchauhan@...tanamicro.com>
Talking with Anup, it sounds like you're planning an updated version of
this one, so will hold off on it.
- Paul
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