[<prev] [next>] [<thread-prev] [day] [month] [year] [list]
Message-ID: <CAPd4WexedtEx7g4bYVB5LpjZGUQV2YCGWw-Bq8_njRzAh5MedA@mail.gmail.com>
Date: Thu, 27 Nov 2025 15:47:15 +0530
From: Himanshu Chauhan <hchauhan@...tanamicro.com>
To: Paul Walmsley <pjw@...nel.org>
Cc: paul.walmsley@...ive.com, palmer@...belt.com, aou@...s.berkeley.edu,
linux-riscv@...ts.infradead.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH v1 2/2] riscv: Introduce support for hardware break/watchpoints
Hi Paul,
On Thu, Nov 27, 2025 at 6:19 AM Paul Walmsley <pjw@...nel.org> wrote:
>
> On Thu, 10 Jul 2025, Himanshu Chauhan wrote:
>
> > RISC-V hardware breakpoint framework is built on top of perf subsystem
> > and uses SBI debug trigger extension to
> > install/uninstall/update/enable/disable hardware triggers as specified
> > in Sdtrig ISA extension.
> >
> > Signed-off-by: Himanshu Chauhan <hchauhan@...tanamicro.com>
>
> Talking with Anup, it sounds like you're planning an updated version of
> this one, so will hold off on it.
That's correct. You can hold this version. I will be posting v2 for
this series which you can target for 6.20.
Regards
Himanshu
>
>
> - Paul
Powered by blists - more mailing lists