lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID:
 <TY3PR01MB1134698D8E9CF61DB44D2B0E786DCA@TY3PR01MB11346.jpnprd01.prod.outlook.com>
Date: Fri, 28 Nov 2025 15:12:14 +0000
From: Biju Das <biju.das.jz@...renesas.com>
To: geert <geert@...ux-m68k.org>
CC: magnus.damm <magnus.damm@...il.com>, Rob Herring <robh@...nel.org>,
	Krzysztof Kozlowski <krzk+dt@...nel.org>, Conor Dooley <conor+dt@...nel.org>,
	"linux-renesas-soc@...r.kernel.org" <linux-renesas-soc@...r.kernel.org>,
	"devicetree@...r.kernel.org" <devicetree@...r.kernel.org>,
	"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>, Prabhakar
 Mahadev Lad <prabhakar.mahadev-lad.rj@...renesas.com>, biju.das.au
	<biju.das.au@...il.com>
Subject: RE: [PATCH 17/19] arm64: dts: renesas: r9a09g047: Add RSCI nodes

Hi Geert,

Thanks for the feedback.

> -----Original Message-----
> From: Geert Uytterhoeven <geert@...ux-m68k.org>
> Sent: 28 November 2025 13:05
> Subject: Re: [PATCH 17/19] arm64: dts: renesas: r9a09g047: Add RSCI nodes
> 
> Hi Biju,
> 
> On Mon, 27 Oct 2025 at 16:47, Biju Das <biju.das.jz@...renesas.com> wrote:
> > Add RSCI nodes to RZ/G3E ("R9A09G047") SoC DTSI.
> >
> > Signed-off-by: Biju Das <biju.das.jz@...renesas.com>
> 
> Thanks for your patch!
> 
> > --- a/arch/arm64/boot/dts/renesas/r9a09g047.dtsi
> > +++ b/arch/arm64/boot/dts/renesas/r9a09g047.dtsi
> > @@ -823,6 +823,196 @@ i2c8: i2c@...01000 {
> >                         status = "disabled";
> >                 };
> >
> > +               rsci0: serial@...00c00 {
> > +                       compatible = "renesas,r9a09g047-rscif";
> 
> "renesas,r9a09g047-rsci", as per the updated DT bindings.

OK.

> 
> > +                       reg = <0 0x12800c00 0 0x400>;
> > +                       interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
> > +                                    <GIC_SPI 115 IRQ_TYPE_EDGE_RISING>,
> > +                                    <GIC_SPI 116 IRQ_TYPE_EDGE_RISING>,
> > +                                    <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
> > +                       interrupt-names = "eri", "rxi", "txi", "tei";
> 
> Missing "aed" and "bfd" interrupts, as per to-be-updated DT bindings.

OK.

> 
> > +                       clocks = <&cpg CPG_MOD 93>, <&cpg CPG_MOD 94>,
> > +                                <&cpg CPG_MOD 95>, <&cpg CPG_MOD 96>,
> > +                                <&cpg CPG_MOD 97>;
> > +                       clock-names = "bus", "tclk", "tclk_div64",
> > +                                     "tclk_div16", "tclk_div4";
> 
> Third and fifth clock and clock name should be exchanged, as per the updated DT bindings.

OK.
> 
> > +                       power-domains = <&cpg>;
> > +                       resets = <&cpg 129>, <&cpg 130>;
> 
> Please use hexadecimal numbers for module clocks and resets, for easier matching with the
> documentation.

Agreed, Will fix this in next version.

Cheers,
Biju

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ