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Message-ID: <20251203-shrew-of-original-tempering-8a8cfc@quoll>
Date: Wed, 3 Dec 2025 09:23:53 +0100
From: Krzysztof Kozlowski <krzk@...nel.org>
To: Tommaso Merciai <tommaso.merciai.xr@...renesas.com>
Cc: tomm.merciai@...il.com, linux-renesas-soc@...r.kernel.org,
biju.das.jz@...renesas.com, Andrzej Hajda <andrzej.hajda@...el.com>,
Neil Armstrong <neil.armstrong@...aro.org>, Robert Foss <rfoss@...nel.org>,
Laurent Pinchart <Laurent.pinchart@...asonboard.com>, Jonas Karlman <jonas@...boo.se>,
Jernej Skrabec <jernej.skrabec@...il.com>, David Airlie <airlied@...il.com>,
Simona Vetter <simona@...ll.ch>, Maarten Lankhorst <maarten.lankhorst@...ux.intel.com>,
Maxime Ripard <mripard@...nel.org>, Thomas Zimmermann <tzimmermann@...e.de>,
Rob Herring <robh@...nel.org>, Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>, Geert Uytterhoeven <geert+renesas@...der.be>,
Michael Turquette <mturquette@...libre.com>, Stephen Boyd <sboyd@...nel.org>,
Magnus Damm <magnus.damm@...il.com>, dri-devel@...ts.freedesktop.org, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org, linux-clk@...r.kernel.org
Subject: Re: [PATCH 10/22] dt-bindings: display: renesas,rzg2l-du: Add
support for RZ/G3E SoC
On Wed, Nov 26, 2025 at 03:07:22PM +0100, Tommaso Merciai wrote:
> The RZ/G3E Soc has 2 LCD controller (LCDC), contain a Frame Compression
> Processor (FCPVD), a Video Signal Processor (VSPD), Video Signal
> Processor (VSPD), and Display Unit (DU).
>
> - LCDC0 supports DSI and LVDS (single or dual-channel) outputs.
> - LCDC1 supports DSI, LVDS (single-channel), and RGB outputs.
>
> Add then two new SoC-specific compatible strings 'renesas,r9a09g047-du0'
> and 'renesas,r9a09g047-du1'.
LCDC0/1 but compatibles du0/du1...
What are the differences between DU0 and DU1? Just different outputs? Is
the programming model the same?
Best regards,
Krzysztof
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