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Message-ID: <176488420978.2206697.11201292177123636920.robh@kernel.org>
Date: Thu, 4 Dec 2025 15:36:50 -0600
From: "Rob Herring (Arm)" <robh@...nel.org>
To: Khairul Anuar Romli <khairul.anuar.romli@...era.com>
Cc: Niravkumar L Rabara <niravkumar.l.rabara@...el.com>,
	Vinod Koul <vkoul@...nel.org>, linux-kernel@...r.kernel.org,
	Eugeniy Paltsev <Eugeniy.Paltsev@...opsys.com>,
	devicetree@...r.kernel.org, Vignesh Raghavendra <vigneshr@...com>,
	Dinh Nguyen <dinguyen@...nel.org>,
	Miquel Raynal <miquel.raynal@...tlin.com>,
	dmaengine@...r.kernel.org, Richard Weinberger <richard@....at>,
	Conor Dooley <conor+dt@...nel.org>,
	Krzysztof Kozlowski <krzk+dt@...nel.org>,
	linux-mtd@...ts.infradead.org
Subject: Re: [PATCH v2 2/3] dt-bindings: dma: snps,dw-axi-dmac: add
 dma-coherent property


On Wed, 03 Dec 2025 07:47:34 +0800, Khairul Anuar Romli wrote:
> The Synopsys DesignWare AXI DMA Controller on Agilex5, the controller
> operates on a cache-coherent AXI interface, where DMA transactions are
> automatically kept coherent with the CPU caches. In previous generations
> SoC (Stratix10 and Agilex) the interconnect was non-coherent, hence there
> is no need for dma-coherent property to be presence. In Agilex 5, the
> architecture has changed. It  introduced a coherent interconnect that
> supports cache-coherent DMA.
> 
> Signed-off-by: Khairul Anuar Romli <khairul.anuar.romli@...era.com>
> ---
> Changes in v2:
>         - Rephrase commit message to describe why the property is needed now
>           and was not needed previously.
>         - Remove redundant statement.
> ---
>  Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml | 2 ++
>  1 file changed, 2 insertions(+)
> 

Reviewed-by: Rob Herring (Arm) <robh@...nel.org>


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