linux-kernel - Re: [PATCH v6 2/2] riscv: add HARDLOCKUP_DETECTOR

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Message-Id: <96fd2a69-baf4-4109-8341-0d4bb6c60393@picoheart.com>
Date: Fri, 5 Dec 2025 14:12:33 +0800
From: "Yicong Yang" <yang.yicong@...oheart.com>
To: "Yunhui Cui" <cuiyunhui@...edance.com>
Cc: <akpm@...ux-foundation.org>, <alex@...ti.fr>, <anup@...infault.org>, 
	<aou@...s.berkeley.edu>, <atish.patra@...ux.dev>, 
	<catalin.marinas@....com>, <dianders@...omium.org>, 
	<johannes@...solutions.net>, <lihuafei1@...wei.com>, 
	<mark.rutland@....com>, <masahiroy@...nel.org>, <maz@...nel.org>, 
	<mingo@...nel.org>, <nicolas.schier@...ux.dev>, <palmer@...belt.com>, 
	<paul.walmsley@...ive.com>, <suzuki.poulose@....com>, 
	<thorsten.blum@...ux.dev>, <wangjinchao600@...il.com>, <will@...nel.org>, 
	<yangyicong@...ilicon.com>, <zhanjie9@...ilicon.com>, 
	<linux-arm-kernel@...ts.infradead.org>, <linux-kernel@...r.kernel.org>, 
	<linux-perf-users@...r.kernel.org>, <linux-riscv@...ts.infradead.org>, 
	"Paul Walmsley" <pjw@...nel.org>, <yang.yicong@...oheart.com>, 
	<geshijian@...oheart.com>
Subject: Re: [PATCH v6 2/2] riscv: add HARDLOCKUP_DETECTOR_PERF support

Hi Yunhui,

this has conflicts on the mainline master. looks like you have a dependency
on the SSE PMU support patchset [1], need to mention it for the maintainer
to apply.

[1] https://lore.kernel.org/linux-riscv/20250908181717.1997461-5-cleger@rivosinc.com/

one comment below.

On 2025/11/14 11:32, Yunhui Cui wrote:
> Enable the HARDLOCKUP_DETECTOR_PERF function based on RISC-V SSE.
> 
> Signed-off-by: Yunhui Cui <cuiyunhui@...edance.com>
> Reviewed-by: Douglas Anderson <dianders@...omium.org>
> Acked-by: Paul Walmsley <pjw@...nel.org>
> ---
>  arch/riscv/Kconfig           |  3 +++
>  drivers/perf/riscv_pmu_sbi.c | 10 ++++++++++
>  2 files changed, 13 insertions(+)
> 
> diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
> index fadec20b87a8e..46ccd33732fa8 100644
> --- a/arch/riscv/Kconfig
> +++ b/arch/riscv/Kconfig
> @@ -186,6 +186,9 @@ config RISCV
>  	select HAVE_PAGE_SIZE_4KB
>  	select HAVE_PCI
>  	select HAVE_PERF_EVENTS
> +	select HAVE_PERF_EVENTS_NMI if RISCV_PMU_SBI_SSE
> +	select HAVE_HARDLOCKUP_DETECTOR_PERF if PERF_EVENTS && HAVE_PERF_EVENTS_NMI
> +	select WATCHDOG_PERF_ADJUST_PERIOD if HARDLOCKUP_DETECTOR_PERF
>  	select HAVE_PERF_REGS
>  	select HAVE_PERF_USER_STACK_DUMP
>  	select HAVE_POSIX_CPU_TIMERS_TASK_WORK
> diff --git a/drivers/perf/riscv_pmu_sbi.c b/drivers/perf/riscv_pmu_sbi.c
> index c852f64a50221..0c7c5924687c9 100644
> --- a/drivers/perf/riscv_pmu_sbi.c
> +++ b/drivers/perf/riscv_pmu_sbi.c
> @@ -22,6 +22,7 @@
>  #include <linux/sched/clock.h>
>  #include <linux/soc/andes/irq.h>
>  #include <linux/workqueue.h>
> +#include <linux/nmi.h>
>  
>  #include <asm/errata_list.h>
>  #include <asm/sbi.h>
> @@ -1192,6 +1193,13 @@ static int pmu_sbi_setup_sse(struct riscv_pmu *pmu)
>  }
>  #endif
>  
> +#ifdef CONFIG_HARDLOCKUP_DETECTOR_PERF
> +bool arch_perf_nmi_is_available(void)
> +{
> +	return IS_ENABLED(CONFIG_RISCV_PMU_SBI_SSE);

this looks incorrect per implementation in [1]. we'll fallback to the normal
interrupt if failed to register the SSE event, in which case NMI is not
available for the PMU. Check the kconfig is not sufficient.

you can check pmu->sse_evt instead for the NMI support here, or cached the
NMI status somewhere like how arm_pmu does.

Thanks.

> +}
> +#endif
> +
>  static int pmu_sbi_starting_cpu(unsigned int cpu, struct hlist_node *node)
>  {
>  	struct riscv_pmu *pmu = hlist_entry_safe(node, struct riscv_pmu, node);
> @@ -1618,6 +1626,8 @@ static int __init pmu_sbi_devinit(void)
>  	/* Notify legacy implementation that SBI pmu is available*/
>  	riscv_pmu_legacy_skip_init();
>  
> +	lockup_detector_retry_init();
> +
>  	return ret;
>  }
>  device_initcall(pmu_sbi_devinit)