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Message-ID: <b7fac86c-15fd-400b-955a-c331c8bc681d@oss.qualcomm.com>
Date: Fri, 5 Dec 2025 10:54:34 +0100
From: Konrad Dybcio <konrad.dybcio@....qualcomm.com>
To: david@...t.cz, Robert Foss <rfoss@...nel.org>,
Todor Tomov <todor.too@...il.com>,
Bryan O'Donoghue <bryan.odonoghue@...aro.org>,
Vladimir Zapolskiy <vladimir.zapolskiy@...aro.org>,
Mauro Carvalho Chehab <mchehab@...nel.org>,
Luca Weiss <luca.weiss@...rphone.com>,
Petr Hodina <phodina@...tonmail.com>,
Casey Connolly <casey.connolly@...aro.org>,
"Dr. Git" <drgitx@...il.com>
Cc: Joel Selvaraj <foss@...lselvaraj.com>,
Kieran Bingham <kbingham@...nel.org>,
Sakari Ailus <sakari.ailus@...ux.intel.com>,
linux-media@...r.kernel.org, linux-arm-msm@...r.kernel.org,
linux-kernel@...r.kernel.org, phone-devel@...r.kernel.org
Subject: Re: [PATCH WIP v2 5/8] media: qcom: camss: csiphy-3ph: Add Gen2 v1.1
MIPI CSI-2 CPHY init
On 12/4/25 5:32 PM, David Heidelberg via B4 Relay wrote:
> From: Casey Connolly <casey.connolly@...aro.org>
>
> Add a PHY configuration sequence for the sdm845 which uses a Qualcomm
> Gen 2 version 1.1 CSI-2 PHY.
>
> The PHY can be configured as two phase or three phase in C-PHY or D-PHY
> mode. This configuration supports three-phase C-PHY mode.
>
> Signed-off-by: Casey Connolly <casey.connolly@...aro.org>
> Reviewed-by: Vladimir Zapolskiy <vladimir.zapolskiy@...aro.org>
> Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@...aro.org>
> Co-developed-by: David Heidelberg <david@...t.cz>
> Signed-off-by: David Heidelberg <david@...t.cz>
> ---
> .../platform/qcom/camss/camss-csiphy-3ph-1-0.c | 74 +++++++++++++++++++++-
> 1 file changed, 72 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c b/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c
> index 3d30cdce33f96..7121aa97a19c4 100644
> --- a/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c
> +++ b/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c
> @@ -145,6 +145,7 @@ csiphy_lane_regs lane_regs_sa8775p[] = {
> };
>
> /* GEN2 1.0 2PH */
> +/* 5 entries: clock + 4 lanes */
> static const struct
> csiphy_lane_regs lane_regs_sdm845[] = {
> {0x0004, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS},
> @@ -219,6 +220,69 @@ csiphy_lane_regs lane_regs_sdm845[] = {
> {0x0664, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS},
> };
>
> +/* GEN2 1.0 3PH */
> +/* 3 entries: 3 lanes (C-PHY) */
> +static const struct
> +csiphy_lane_regs lane_regs_sdm845_3ph[] = {
Here's a downstream snippet which seems to have more up-to-date settings
(checked against a doc and it seems to have changes made at the time of
the last edit of the doc)
You'll notice it's split into 3 arrays of register sets - that's because
it applies setting for each lane.. something to keep in mind we could
optimize upstream data storage for (they are identical per lane in this
instance) one day
struct csiphy_reg_t csiphy_3ph_v1_0_reg[MAX_LANES][MAX_SETTINGS_PER_LANE] = {
{
{0x015C, 0x63, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0168, 0xAC, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x016C, 0xA5, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0104, 0x06, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x010C, 0x12, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE},
{0x0108, 0x00, 0x00, CSIPHY_SETTLE_CNT_HIGHER_BYTE},
{0x0114, 0x20, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0150, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0118, 0x3e, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x011C, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0120, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0124, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0128, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x012C, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0144, 0x12, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0160, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x01CC, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0164, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x01DC, 0x51, 0x00, CSIPHY_DEFAULT_PARAMS},
},
{
{0x035C, 0x63, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0368, 0xAC, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x036C, 0xA5, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0304, 0x06, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x030C, 0x12, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE},
{0x0308, 0x00, 0x00, CSIPHY_SETTLE_CNT_HIGHER_BYTE},
{0x0314, 0x20, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0350, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0318, 0x3e, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x031C, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0320, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0324, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0328, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x032C, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0344, 0x12, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0360, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x03CC, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0364, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x03DC, 0x51, 0x00, CSIPHY_DEFAULT_PARAMS},
},
{
{0x055C, 0x63, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0568, 0xAC, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x056C, 0xA5, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0504, 0x06, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x050C, 0x12, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE},
{0x0508, 0x00, 0x00, CSIPHY_SETTLE_CNT_HIGHER_BYTE},
{0x0514, 0x20, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0550, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0518, 0x3e, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x051C, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0520, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0524, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0528, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x052C, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0544, 0x12, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0560, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x05CC, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0564, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x05DC, 0x51, 0x00, CSIPHY_DEFAULT_PARAMS},
},
};
Konrad
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