linux-kernel - Re: [PATCH WIP v2 5/8] media: qcom: camss: csiphy-3ph: Add Gen2 v1.1 MIPI CSI-2 CPHY init

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Message-ID: <03c137aa-bd31-43d7-aea8-489ec0102ab3@ixit.cz>
Date: Fri, 5 Dec 2025 12:56:15 +0100
From: David Heidelberg <david@...t.cz>
To: Konrad Dybcio <konrad.dybcio@....qualcomm.com>,
 Robert Foss <rfoss@...nel.org>, Todor Tomov <todor.too@...il.com>,
 Bryan O'Donoghue <bryan.odonoghue@...aro.org>,
 Vladimir Zapolskiy <vladimir.zapolskiy@...aro.org>,
 Mauro Carvalho Chehab <mchehab@...nel.org>,
 Luca Weiss <luca.weiss@...rphone.com>, Petr Hodina <phodina@...tonmail.com>,
 Casey Connolly <casey.connolly@...aro.org>, "Dr. Git" <drgitx@...il.com>
Cc: Joel Selvaraj <foss@...lselvaraj.com>,
 Kieran Bingham <kbingham@...nel.org>,
 Sakari Ailus <sakari.ailus@...ux.intel.com>, linux-media@...r.kernel.org,
 linux-arm-msm@...r.kernel.org, linux-kernel@...r.kernel.org,
 phone-devel@...r.kernel.org
Subject: Re: [PATCH WIP v2 5/8] media: qcom: camss: csiphy-3ph: Add Gen2 v1.1
 MIPI CSI-2 CPHY init

On 05/12/2025 10:54, Konrad Dybcio wrote:
> On 12/4/25 5:32 PM, David Heidelberg via B4 Relay wrote:
>> From: Casey Connolly <casey.connolly@...aro.org>
>>
>> Add a PHY configuration sequence for the sdm845 which uses a Qualcomm
>> Gen 2 version 1.1 CSI-2 PHY.
>>
>> The PHY can be configured as two phase or three phase in C-PHY or D-PHY
>> mode. This configuration supports three-phase C-PHY mode.
>>
>> Signed-off-by: Casey Connolly <casey.connolly@...aro.org>
>> Reviewed-by: Vladimir Zapolskiy <vladimir.zapolskiy@...aro.org>
>> Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@...aro.org>
>> Co-developed-by: David Heidelberg <david@...t.cz>
>> Signed-off-by: David Heidelberg <david@...t.cz>
>> ---
>>   .../platform/qcom/camss/camss-csiphy-3ph-1-0.c     | 74 +++++++++++++++++++++-
>>   1 file changed, 72 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c b/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c
>> index 3d30cdce33f96..7121aa97a19c4 100644
>> --- a/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c
>> +++ b/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c
>> @@ -145,6 +145,7 @@ csiphy_lane_regs lane_regs_sa8775p[] = {
>>   };
>>   
>>   /* GEN2 1.0 2PH */
>> +/* 5 entries: clock + 4 lanes */
>>   static const struct
>>   csiphy_lane_regs lane_regs_sdm845[] = {
>>   	{0x0004, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS},
>> @@ -219,6 +220,69 @@ csiphy_lane_regs lane_regs_sdm845[] = {
>>   	{0x0664, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS},
>>   };
>>   
>> +/* GEN2 1.0 3PH */
>> +/* 3 entries: 3 lanes (C-PHY) */
>> +static const struct
>> +csiphy_lane_regs lane_regs_sdm845_3ph[] = {
> 
> Here's a downstream snippet which seems to have more up-to-date settings
> (checked against a doc and it seems to have changes made at the time of
> the last edit of the doc)
> 
> You'll notice it's split into 3 arrays of register sets - that's because
> it applies setting for each lane.. something to keep in mind we could
> optimize upstream data storage for (they are identical per lane in this
> instance) one day

see 87c2c2716523 ("media: qcom: camss: csiphy-3ph: Remove redundant PHY 
init sequence control loop")

for the reason to flatten the regs array (thou outside the scope of this 
patchset).

Regarding to the different value, I can test them, can you point to docs 
regarding why these regs has been changed and what the values means?

I thought it's some default seq, but as you show there is multiple 
versions, it make sense to properly document what these regs do.

David
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