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Message-ID: <20251208101356.101379-2-biju.das.jz@bp.renesas.com>
Date: Mon, 8 Dec 2025 10:13:33 +0000
From: Biju <biju.das.au@...il.com>
To: Geert Uytterhoeven <geert+renesas@...der.be>,
Michael Turquette <mturquette@...libre.com>,
Philipp Zabel <p.zabel@...gutronix.de>,
Stephen Boyd <sboyd@...nel.org>
Cc: Biju Das <biju.das.jz@...renesas.com>,
linux-renesas-soc@...r.kernel.org,
linux-clk@...r.kernel.org,
linux-kernel@...r.kernel.org,
Prabhakar Mahadev Lad <prabhakar.mahadev-lad.rj@...renesas.com>,
Biju Das <biju.das.au@...il.com>
Subject: [PATCH 1/2] clk: renesas: rzg2l: Deassert reset on assert timeout
From: Biju Das <biju.das.jz@...renesas.com>
If the assert() fails due to timeout error, set the reset register bit
back to deasserted state. This change is needed especially for handling
assert error in suspend() callback that expect the device to be in
operational state in case of failure.
Signed-off-by: Biju Das <biju.das.jz@...renesas.com>
---
drivers/clk/renesas/rzg2l-cpg.c | 5 ++++-
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/renesas/rzg2l-cpg.c b/drivers/clk/renesas/rzg2l-cpg.c
index 64d1ef6e4c94..751f0340854f 100644
--- a/drivers/clk/renesas/rzg2l-cpg.c
+++ b/drivers/clk/renesas/rzg2l-cpg.c
@@ -1669,8 +1669,11 @@ static int __rzg2l_cpg_assert(struct reset_controller_dev *rcdev,
ret = readl_poll_timeout_atomic(priv->base + reg, value,
assert == !!(value & mask), 10, 200);
- if (ret && !assert) {
+ if (ret) {
value = mask << 16;
+ if (assert)
+ value |= mask;
+
writel(value, priv->base + CLK_RST_R(info->resets[id].off));
}
--
2.43.0
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