linux-kernel - Re: [PATCH 2/2] clk: renesas: rzv2h: Deassert reset on assert timeout

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Message-ID: <88cdf9195a8bf397ff631d316d9f6560f2cbab5c.camel@pengutronix.de>
Date: Mon, 08 Dec 2025 12:21:39 +0100
From: Philipp Zabel <p.zabel@...gutronix.de>
To: Biju <biju.das.au@...il.com>, Geert Uytterhoeven
 <geert+renesas@...der.be>,  Michael Turquette <mturquette@...libre.com>,
 Stephen Boyd <sboyd@...nel.org>
Cc: Biju Das <biju.das.jz@...renesas.com>,
 linux-renesas-soc@...r.kernel.org, 	linux-clk@...r.kernel.org,
 linux-kernel@...r.kernel.org, Prabhakar Mahadev Lad	
 <prabhakar.mahadev-lad.rj@...renesas.com>
Subject: Re: [PATCH 2/2] clk: renesas: rzv2h: Deassert reset on assert
 timeout

On Mo, 2025-12-08 at 10:13 +0000, Biju wrote:
> From: Biju Das <biju.das.jz@...renesas.com>
> 
> If the assert() fails due to timeout error, set the reset register bit
> back to deasserted state. This change is needed especially for handling
> assert error in suspend() callback that expect the device to be in
> operational state in case of failure.
> 
> Signed-off-by: Biju Das <biju.das.jz@...renesas.com>
> ---
>  drivers/clk/renesas/rzv2h-cpg.c | 5 ++++-
>  1 file changed, 4 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/clk/renesas/rzv2h-cpg.c b/drivers/clk/renesas/rzv2h-cpg.c
> index 3f6299b9fec0..c0ee2dcc858c 100644
> --- a/drivers/clk/renesas/rzv2h-cpg.c
> +++ b/drivers/clk/renesas/rzv2h-cpg.c
> @@ -1366,8 +1366,11 @@ static int __rzv2h_cpg_assert(struct reset_controller_dev *rcdev,
>  
>  	ret = readl_poll_timeout_atomic(priv->base + reg, value,
>  					assert == !!(value & mask), 10, 200);
> -	if (ret && !assert) {
> +	if (ret) {
>  		value = mask << 16;
> +		if (assert)
> +			value |= mask;
> +
>  		writel(value, priv->base + GET_RST_OFFSET(priv->resets[id].reset_index));

This writel() could reuse

	unsigned int reg = GET_RST_OFFSET(priv->resets[id].reset_index);

>  	}

How does the hardware behave when __rzv2h_cpg_assert() is called on an
already asserted reset? Is it possible for the
readl_poll_timeout_atomic() timeout to trigger, or can this only ever
happen for asserted <-> deasserted transitions? Having a failed
reset_control_assert() deassert the reset if it was previously asserted
would be surprising.

regards
Philipp