linux-kernel - Re: [PATCH 1/3] perf/x86/intel/cstate: Add Wildcat Lake support

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Message-ID: <a01f17ee-7388-4e83-8c02-132f0fc51f1a@linux.intel.com>
Date: Tue, 16 Dec 2025 09:51:36 +0800
From: "Mi, Dapeng" <dapeng1.mi@...ux.intel.com>
To: Zide Chen <zide.chen@...el.com>, Peter Zijlstra <peterz@...radead.org>,
 Ingo Molnar <mingo@...hat.com>, Arnaldo Carvalho de Melo <acme@...nel.org>,
 Namhyung Kim <namhyung@...nel.org>, Ian Rogers <irogers@...gle.com>,
 Adrian Hunter <adrian.hunter@...el.com>,
 Alexander Shishkin <alexander.shishkin@...ux.intel.com>,
 Andi Kleen <ak@...ux.intel.com>, Eranian Stephane <eranian@...gle.com>
Cc: linux-kernel@...r.kernel.org, linux-perf-users@...r.kernel.org,
 Artem Bityutskiy <artem.bityutskiy@...ux.intel.com>,
 Srinivas Pandruvada <srinivas.pandruvada@...ux.intel.com>,
 Xudong Hao <xudong.hao@...el.com>, Falcon Thomas <thomas.falcon@...el.com>
Subject: Re: [PATCH 1/3] perf/x86/intel/cstate: Add Wildcat Lake support

The whole patch-set looks good to me. Thanks.

Reviewed-by: Dapeng Mi <dapeng1.mi@...ux.intel.com>


On 12/16/2025 2:25 AM, Zide Chen wrote:
> Wildcat Lake (WCL) is a low-power variant of Panther Lake.  From a
> C-state profiling perspective, it supports the same residency counters:
> CC1/CC6/CC7 and PC2/PC6/PC10.
>
> Signed-off-by: Zide Chen <zide.chen@...el.com>
> ---
>  arch/x86/events/intel/cstate.c | 14 ++++++++------
>  1 file changed, 8 insertions(+), 6 deletions(-)
>
> diff --git a/arch/x86/events/intel/cstate.c b/arch/x86/events/intel/cstate.c
> index fa67fda6e45b..b719b0a68a2a 100644
> --- a/arch/x86/events/intel/cstate.c
> +++ b/arch/x86/events/intel/cstate.c
> @@ -41,7 +41,7 @@
>   *	MSR_CORE_C1_RES: CORE C1 Residency Counter
>   *			 perf code: 0x00
>   *			 Available model: SLM,AMT,GLM,CNL,ICX,TNT,ADL,RPL
> - *					  MTL,SRF,GRR,ARL,LNL,PTL
> + *					  MTL,SRF,GRR,ARL,LNL,PTL,WCL
>   *			 Scope: Core (each processor core has a MSR)
>   *	MSR_CORE_C3_RESIDENCY: CORE C3 Residency Counter
>   *			       perf code: 0x01
> @@ -53,19 +53,19 @@
>   *			       Available model: SLM,AMT,NHM,WSM,SNB,IVB,HSW,BDW,
>   *						SKL,KNL,GLM,CNL,KBL,CML,ICL,ICX,
>   *						TGL,TNT,RKL,ADL,RPL,SPR,MTL,SRF,
> - *						GRR,ARL,LNL,PTL
> + *						GRR,ARL,LNL,PTL,WCL
>   *			       Scope: Core
>   *	MSR_CORE_C7_RESIDENCY: CORE C7 Residency Counter
>   *			       perf code: 0x03
>   *			       Available model: SNB,IVB,HSW,BDW,SKL,CNL,KBL,CML,
>   *						ICL,TGL,RKL,ADL,RPL,MTL,ARL,LNL,
> - *						PTL
> + *						PTL,WCL
>   *			       Scope: Core
>   *	MSR_PKG_C2_RESIDENCY:  Package C2 Residency Counter.
>   *			       perf code: 0x00
>   *			       Available model: SNB,IVB,HSW,BDW,SKL,KNL,GLM,CNL,
>   *						KBL,CML,ICL,ICX,TGL,TNT,RKL,ADL,
> - *						RPL,SPR,MTL,ARL,LNL,SRF,PTL
> + *						RPL,SPR,MTL,ARL,LNL,SRF,PTL,WCL
>   *			       Scope: Package (physical package)
>   *	MSR_PKG_C3_RESIDENCY:  Package C3 Residency Counter.
>   *			       perf code: 0x01
> @@ -78,7 +78,7 @@
>   *			       Available model: SLM,AMT,NHM,WSM,SNB,IVB,HSW,BDW,
>   *						SKL,KNL,GLM,CNL,KBL,CML,ICL,ICX,
>   *						TGL,TNT,RKL,ADL,RPL,SPR,MTL,SRF,
> - *						ARL,LNL,PTL
> + *						ARL,LNL,PTL,WCL
>   *			       Scope: Package (physical package)
>   *	MSR_PKG_C7_RESIDENCY:  Package C7 Residency Counter.
>   *			       perf code: 0x03
> @@ -97,7 +97,8 @@
>   *	MSR_PKG_C10_RESIDENCY: Package C10 Residency Counter.
>   *			       perf code: 0x06
>   *			       Available model: HSW ULT,KBL,GLM,CNL,CML,ICL,TGL,
> - *						TNT,RKL,ADL,RPL,MTL,ARL,LNL,PTL
> + *						TNT,RKL,ADL,RPL,MTL,ARL,LNL,PTL,
> + *						WCL
>   *			       Scope: Package (physical package)
>   *	MSR_MODULE_C6_RES_MS:  Module C6 Residency Counter.
>   *			       perf code: 0x00
> @@ -654,6 +655,7 @@ static const struct x86_cpu_id intel_cstates_match[] __initconst = {
>  	X86_MATCH_VFM(INTEL_ARROWLAKE_U,	&adl_cstates),
>  	X86_MATCH_VFM(INTEL_LUNARLAKE_M,	&lnl_cstates),
>  	X86_MATCH_VFM(INTEL_PANTHERLAKE_L,	&lnl_cstates),
> +	X86_MATCH_VFM(INTEL_WILDCATLAKE_L,	&lnl_cstates),
>  	{ },
>  };
>  MODULE_DEVICE_TABLE(x86cpu, intel_cstates_match);