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Message-ID: <176589292037.510.1492747132077966710.tip-bot2@tip-bot2>
Date: Tue, 16 Dec 2025 13:48:40 -0000
From: "tip-bot2 for Zide Chen" <tip-bot2@...utronix.de>
To: linux-tip-commits@...r.kernel.org
Cc: Zide Chen <zide.chen@...el.com>, Ingo Molnar <mingo@...nel.org>,
Dapeng Mi <dapeng1.mi@...ux.intel.com>, x86@...nel.org,
linux-kernel@...r.kernel.org
Subject: [tip: perf/core] perf/x86/intel/cstate: Add Wildcat Lake support
The following commit has been merged into the perf/core branch of tip:
Commit-ID: 6d4b8d052ff22742c3980fa45f26b0969a9b6163
Gitweb: https://git.kernel.org/tip/6d4b8d052ff22742c3980fa45f26b0969a9b6163
Author: Zide Chen <zide.chen@...el.com>
AuthorDate: Mon, 15 Dec 2025 10:25:18 -08:00
Committer: Ingo Molnar <mingo@...nel.org>
CommitterDate: Tue, 16 Dec 2025 14:35:59 +01:00
perf/x86/intel/cstate: Add Wildcat Lake support
Wildcat Lake (WCL) is a low-power variant of Panther Lake. From a
C-state profiling perspective, it supports the same residency counters:
CC1/CC6/CC7 and PC2/PC6/PC10.
Signed-off-by: Zide Chen <zide.chen@...el.com>
Signed-off-by: Ingo Molnar <mingo@...nel.org>
Reviewed-by: Dapeng Mi <dapeng1.mi@...ux.intel.com>
Link: https://patch.msgid.link/20251215182520.115822-1-zide.chen@intel.com
---
arch/x86/events/intel/cstate.c | 14 ++++++++------
1 file changed, 8 insertions(+), 6 deletions(-)
diff --git a/arch/x86/events/intel/cstate.c b/arch/x86/events/intel/cstate.c
index fa67fda..b719b0a 100644
--- a/arch/x86/events/intel/cstate.c
+++ b/arch/x86/events/intel/cstate.c
@@ -41,7 +41,7 @@
* MSR_CORE_C1_RES: CORE C1 Residency Counter
* perf code: 0x00
* Available model: SLM,AMT,GLM,CNL,ICX,TNT,ADL,RPL
- * MTL,SRF,GRR,ARL,LNL,PTL
+ * MTL,SRF,GRR,ARL,LNL,PTL,WCL
* Scope: Core (each processor core has a MSR)
* MSR_CORE_C3_RESIDENCY: CORE C3 Residency Counter
* perf code: 0x01
@@ -53,19 +53,19 @@
* Available model: SLM,AMT,NHM,WSM,SNB,IVB,HSW,BDW,
* SKL,KNL,GLM,CNL,KBL,CML,ICL,ICX,
* TGL,TNT,RKL,ADL,RPL,SPR,MTL,SRF,
- * GRR,ARL,LNL,PTL
+ * GRR,ARL,LNL,PTL,WCL
* Scope: Core
* MSR_CORE_C7_RESIDENCY: CORE C7 Residency Counter
* perf code: 0x03
* Available model: SNB,IVB,HSW,BDW,SKL,CNL,KBL,CML,
* ICL,TGL,RKL,ADL,RPL,MTL,ARL,LNL,
- * PTL
+ * PTL,WCL
* Scope: Core
* MSR_PKG_C2_RESIDENCY: Package C2 Residency Counter.
* perf code: 0x00
* Available model: SNB,IVB,HSW,BDW,SKL,KNL,GLM,CNL,
* KBL,CML,ICL,ICX,TGL,TNT,RKL,ADL,
- * RPL,SPR,MTL,ARL,LNL,SRF,PTL
+ * RPL,SPR,MTL,ARL,LNL,SRF,PTL,WCL
* Scope: Package (physical package)
* MSR_PKG_C3_RESIDENCY: Package C3 Residency Counter.
* perf code: 0x01
@@ -78,7 +78,7 @@
* Available model: SLM,AMT,NHM,WSM,SNB,IVB,HSW,BDW,
* SKL,KNL,GLM,CNL,KBL,CML,ICL,ICX,
* TGL,TNT,RKL,ADL,RPL,SPR,MTL,SRF,
- * ARL,LNL,PTL
+ * ARL,LNL,PTL,WCL
* Scope: Package (physical package)
* MSR_PKG_C7_RESIDENCY: Package C7 Residency Counter.
* perf code: 0x03
@@ -97,7 +97,8 @@
* MSR_PKG_C10_RESIDENCY: Package C10 Residency Counter.
* perf code: 0x06
* Available model: HSW ULT,KBL,GLM,CNL,CML,ICL,TGL,
- * TNT,RKL,ADL,RPL,MTL,ARL,LNL,PTL
+ * TNT,RKL,ADL,RPL,MTL,ARL,LNL,PTL,
+ * WCL
* Scope: Package (physical package)
* MSR_MODULE_C6_RES_MS: Module C6 Residency Counter.
* perf code: 0x00
@@ -654,6 +655,7 @@ static const struct x86_cpu_id intel_cstates_match[] __initconst = {
X86_MATCH_VFM(INTEL_ARROWLAKE_U, &adl_cstates),
X86_MATCH_VFM(INTEL_LUNARLAKE_M, &lnl_cstates),
X86_MATCH_VFM(INTEL_PANTHERLAKE_L, &lnl_cstates),
+ X86_MATCH_VFM(INTEL_WILDCATLAKE_L, &lnl_cstates),
{ },
};
MODULE_DEVICE_TABLE(x86cpu, intel_cstates_match);
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