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Message-ID: <176597508125.510.7955284109554841354.tip-bot2@tip-bot2> Date: Wed, 17 Dec 2025 12:38:01 -0000 From: "tip-bot2 for Martin Schiller" <tip-bot2@...utronix.de> To: linux-tip-commits@...r.kernel.org Cc: Martin Schiller <ms@....tdt.de>, "Peter Zijlstra (Intel)" <peterz@...radead.org>, Dapeng Mi <dapeng1.mi@...ux.intel.com>, x86@...nel.org, linux-kernel@...r.kernel.org Subject: [tip: perf/core] perf/x86/msr: Add Airmont NP The following commit has been merged into the perf/core branch of tip: Commit-ID: 63dbadcafc1f4d1da796a8e2c0aea1e561f79ece Gitweb: https://git.kernel.org/tip/63dbadcafc1f4d1da796a8e2c0aea1e561f79ece Author: Martin Schiller <ms@....tdt.de> AuthorDate: Mon, 24 Nov 2025 08:48:44 +01:00 Committer: Peter Zijlstra <peterz@...radead.org> CommitterDate: Wed, 17 Dec 2025 13:31:08 +01:00 perf/x86/msr: Add Airmont NP Like Airmont, the Airmont NP (aka Intel / MaxLinear Lightning Mountain) supports SMI_COUNT MSR. Signed-off-by: Martin Schiller <ms@....tdt.de> Signed-off-by: Peter Zijlstra (Intel) <peterz@...radead.org> Reviewed-by: Dapeng Mi <dapeng1.mi@...ux.intel.com> Link: https://patch.msgid.link/20251124074846.9653-2-ms@dev.tdt.de --- arch/x86/events/msr.c | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/x86/events/msr.c b/arch/x86/events/msr.c index 7f5007a..8052596 100644 --- a/arch/x86/events/msr.c +++ b/arch/x86/events/msr.c @@ -78,6 +78,7 @@ static bool test_intel(int idx, void *data) case INTEL_ATOM_SILVERMONT: case INTEL_ATOM_SILVERMONT_D: case INTEL_ATOM_AIRMONT: + case INTEL_ATOM_AIRMONT_NP: case INTEL_ATOM_GOLDMONT: case INTEL_ATOM_GOLDMONT_D:
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