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Message-Id: <7A2ADADA-3FD8-4AAE-B7D8-9137399FBE6E@probably.group>
Date: Thu, 18 Dec 2025 00:31:18 +0100
From: "Martin Holovský (Probably Nothing s.r.o.)" <mh@...bably.group>
To: Heiko Stuebner <heiko@...ech.de>
Cc: Rob Herring <robh@...nel.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>,
devicetree@...r.kernel.org,
linux-arm-kernel@...ts.infradead.org,
linux-rockchip@...ts.infradead.org,
linux-kernel@...r.kernel.org
Subject: Re: [PATCH] arm64: dts: rockchip: enable dual 2.5GbE on Rock 5T
Perfect, thanks a lot!
> On 15. 12. 2025, at 14:51, Heiko Stuebner <heiko@...ech.de> wrote:
>
>
> On Fri, 12 Dec 2025 17:23:35 +0100, "Martin Holovský (Probably Nothing s.r.o. )" wrote:
>> The Radxa Rock 5T board features two RTL8125B 2.5GbE Ethernet controllers
>> connected via PCIe lanes pcie2x1l0 (fe170000) and pcie2x1l2 (fe190000).
>> Currently only one interface is functional because the PCIe controller
>> nodes lack the necessary reset GPIO configuration.
>>
>> Without the reset-gpios property, the RTL8125B PHYs remain in reset state
>> and are not enumerated by the PCIe bus. This results in only one Ethernet
>> interface being detected, or none at all depending on U-Boot initialization.
>>
>> [...]
>
> Applied, thanks!
>
> [1/1] arm64: dts: rockchip: enable dual 2.5GbE on Rock 5T
> commit: 96029ffeccf677b1e4baa98f30909a83a485b6d7
>
> I've resorted both the pcie phandles as well as the pinctrl entries
> pcie2-0 comes before pcie2-1 etc :-) .
>
> Best regards,
> --
> Heiko Stuebner <heiko@...ech.de>
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