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Message-ID: <1244cf8e-d06c-473d-96a6-2b8e126a45de@nvidia.com>
Date: Thu, 18 Dec 2025 16:51:45 +0000
From: Jon Hunter <jonathanh@...dia.com>
To: Krzysztof Kozlowski <krzk@...nel.org>, Ketan Patil <ketanp@...dia.com>,
 thierry.reding@...il.com
Cc: linux-kernel@...r.kernel.org, linux-tegra@...r.kernel.org
Subject: Re: [PATCH v4 1/4] memory: tegra: Group mc-err related registers


On 18/12/2025 16:17, Krzysztof Kozlowski wrote:
> On 24/11/2025 18:35, Ketan Patil wrote:
>> Group MC error related registers into a struct as they could have soc
>> specific values.
> 
> I do not understand the goal. The values already have "soc specific
> values". Your commit msg should explain why you are doing this and based
> on that explanation that's a no. There is no point in doing this.
Krzysztof is correct. We need to state here that Tegra264 has different 
register offsets that the existing devices and so in order to add 
support for Tegra264 we need to first make this change.

Although in patch 4/4 you add Tegra264, looking at this patch alone the 
reviewer has no idea why we are doing this and it just looks like churn.

-- 
nvpublic


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