lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <162cb2d5-6e1b-44dc-8c4a-facdf2f0de5e@nvidia.com>
Date: Thu, 18 Dec 2025 16:54:30 +0000
From: Jon Hunter <jonathanh@...dia.com>
To: Ketan Patil <ketanp@...dia.com>, krzk@...nel.org, thierry.reding@...il.com
Cc: linux-kernel@...r.kernel.org, linux-tegra@...r.kernel.org
Subject: Re: [PATCH v4 3/4] memory: tegra: Add support for multiple irqs


On 24/11/2025 17:35, Ketan Patil wrote:
> Add support to handle multiple MC interrupts lines as the number of
> interrupt lines could vary based upon SoC. Add field to specify the
> number of interrupts and iterate over the number of interrupts to
> register handler for each interrupt. SoC with multiple interrupts
> will be added in subsequent patches.

Same here. We need to be explicit. The 'could vary' sounds like it is 
theoretically possible. However, what we need to say is that Tegra264 
supports multiple MC interrupt lines and so make the necessary changes 
to the Tegra MC driver to support devices with more than one interrupt 
line.

Jon

-- 
nvpublic


Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ