linux-kernel - Re: [PATCH v2 2/5] openrisc: dts: Add de0 nano config and devicetree

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Message-ID: <CAMuHMdVCY=5UypK65Ver6UZM_m6DZuw9mhfANMx4+Y6PgNAdmA@mail.gmail.com>
Date: Thu, 18 Dec 2025 19:36:08 +0100
From: Geert Uytterhoeven <geert@...ux-m68k.org>
To: Stafford Horne <shorne@...il.com>
Cc: LKML <linux-kernel@...r.kernel.org>, 
	Linux OpenRISC <linux-openrisc@...r.kernel.org>, Rob Herring <robh@...nel.org>, 
	Krzysztof Kozlowski <krzk+dt@...nel.org>, Conor Dooley <conor+dt@...nel.org>, 
	Jonas Bonn <jonas@...thpole.se>, 
	Stefan Kristiansson <stefan.kristiansson@...nalahti.fi>, devicetree@...r.kernel.org
Subject: Re: [PATCH v2 2/5] openrisc: dts: Add de0 nano config and devicetree

Hi Stafford,

On Wed, 17 Dec 2025 at 09:23, Stafford Horne <shorne@...il.com> wrote:
> The de0 nano from Terasic is an FPGA board that we use in the OpenRISC
> community to test OpenRISC configurations.  Add a base configuration for
> the board that runs an OpenRISC CPU at 50Mhz with 32MB ram, UART for
> console and some GPIOs for LEDs and switches.
>
> There is an older version of this floating around that defines all of
> the hardware on the board including SPI's, flash devices, sram, ADCs
> etc.  Eventually it would be good to get the full version upstream
> but for now I think a minimal board is good to start with.
>
> Link: https://openrisc.io/tutorials/de0_nano/
> Link: https://github.com/olofk/de0_nano
>
> Signed-off-by: Stafford Horne <shorne@...il.com>

Thanks for your patch!

> --- /dev/null
> +++ b/arch/openrisc/boot/dts/de0-nano-common.dtsi
> @@ -0,0 +1,41 @@
> +// SPDX-License-Identifier: GPL-2.0
> +
> +#include <dt-bindings/gpio/gpio.h>
> +#include <dt-bindings/leds/common.h>
> +
> +/ {
> +       memory@0 {
> +               device_type = "memory";
> +               reg = <0x00000000 0x02000000>;
> +       };
> +
> +       leds: leds {

Move this up (or down), before (or after) all nodes with unit addresses?

> +               compatible = "gpio-leds";
> +               status = "okay";

Missing blank line.

> +               led-heartbeat {
> +                       gpios = <&gpio0 0 GPIO_ACTIVE_HIGH>;
> +                       color = <LED_COLOR_ID_GREEN>;
> +                       function = LED_FUNCTION_HEARTBEAT;
> +                       linux,default-trigger = "heartbeat";
> +                       label = "heartbeat";
> +               };
> +       };
> +
> +       gpio0: gpio@...00000 {
> +               compatible = "opencores,gpio", "brcm,bcm6345-gpio";
> +               reg = <0x91000000 0x1>, <0x91000001 0x1>;
> +               reg-names = "dat", "dirout";
> +               gpio-controller;
> +               #gpio-cells = <2>;
> +               status = "okay";

"okay" is the default, so you could drop this line.

> +       };
> +
> +       gpio1: gpio@...00000 {
> +               compatible = "opencores,gpio", "brcm,bcm6345-gpio";
> +               reg = <0x92000000 0x1>, <0x92000001 0x1>;
> +               reg-names = "dat", "dirout";
> +               gpio-controller;
> +               #gpio-cells = <2>;
> +               status = "disabled";
> +       };
> +};

> --- /dev/null
> +++ b/arch/openrisc/boot/dts/de0-nano.dts
> @@ -0,0 +1,54 @@
> +// SPDX-License-Identifier: GPL-2.0
> +
> +/dts-v1/;
> +
> +#include "de0-nano-common.dtsi"
> +
> +/ {
> +       model = "Terasic DE0 Nano";
> +       compatible = "opencores,or1ksim";
> +       #address-cells = <1>;
> +       #size-cells = <1>;
> +       interrupt-parent = <&pic>;
> +
> +       aliases {
> +               uart0 = &serial0;
> +       };
> +
> +       chosen {
> +               bootargs = "earlycon";

Do you need this?

> +               stdout-path = "uart0:115200";
> +       };
> +
> +       cpus {
> +               #address-cells = <1>;
> +               #size-cells = <0>;

Missing blank line.

> +               cpu@0 {
> +                       compatible = "opencores,or1200-rtlsvn481";
> +                       reg = <0>;
> +                       clock-frequency = <50000000>;
> +               };
> +       };
> +
> +       /*
> +        * OR1K PIC is built into CPU and accessed via special purpose
> +        * registers.  It is not addressable and, hence, has no 'reg'
> +        * property.
> +        */
> +       pic: pic {
> +               compatible = "opencores,or1k-pic";
> +               #interrupt-cells = <1>;
> +               interrupt-controller;
> +       };
> +
> +       serial0: serial@...00000 {
> +               compatible = "opencores,uart16550-rtlsvn105", "ns16550a";
> +               reg = <0x90000000 0x100>;
> +               interrupts = <2>;
> +               clock-frequency = <50000000>;
> +       };
> +};

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@...ux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds