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Message-ID: <38364cfe-8fc9-4ed7-9034-4e67584ee965@nvidia.com>
Date: Thu, 18 Dec 2025 12:33:52 +0530
From: Ashish Mhetre <amhetre@...dia.com>
To: Jon Hunter <jonathanh@...dia.com>, will@...nel.org, robin.murphy@....com,
joro@...tes.org, robh@...nel.org, krzk+dt@...nel.org, conor+dt@...nel.org,
nicolinc@...dia.com
Cc: thierry.reding@...il.com, vdumpa@...dia.com, jgg@...pe.ca,
linux-arm-kernel@...ts.infradead.org, iommu@...ts.linux.dev,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
linux-tegra@...r.kernel.org
Subject: Re: [PATCH V7 3/4] dt-bindings: iommu: Add NVIDIA Tegra CMDQV support
On 12/18/2025 2:01 AM, Jon Hunter wrote:
>
>
> On 15/12/2025 06:48, Ashish Mhetre wrote:
>> The Command Queue Virtualization (CMDQV) hardware is part of the
>> SMMUv3 implementation on NVIDIA Tegra SoCs. It assists in
>> virtualizing the command queue for the SMMU.
>>
>> Add a new device tree binding document for nvidia,tegra264-cmdqv.
>>
>> Also update the arm,smmu-v3 binding to include an optional nvidia,cmdqv
>> property. This property is a phandle to the CMDQV device node, allowing
>> the SMMU driver to associate with its corresponding CMDQV instance.
>> Restrict this property usage to Nvidia Tegra264 only.
>>
>> Reviewed-by: Rob Herring (Arm) <robh@...nel.org>
>> Signed-off-by: Ashish Mhetre <amhetre@...dia.com>
>> ---
>> .../bindings/iommu/arm,smmu-v3.yaml | 30 ++++++++++++-
>> .../bindings/iommu/nvidia,tegra264-cmdqv.yaml | 42 +++++++++++++++++++
>> 2 files changed, 70 insertions(+), 2 deletions(-)
>> create mode 100644
>> Documentation/devicetree/bindings/iommu/nvidia,tegra264-cmdqv.yaml
>>
>> diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml
>> b/Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml
>> index 75fcf4cb52d9..1c03482e4c61 100644
>> --- a/Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml
>> +++ b/Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml
>> @@ -20,7 +20,12 @@ properties:
>> $nodename:
>> pattern: "^iommu@[0-9a-f]*"
>> compatible:
>> - const: arm,smmu-v3
>> + oneOf:
>> + - const: arm,smmu-v3
>> + - items:
>> + - enum:
>> + - nvidia,tegra264-smmu
>> + - const: arm,smmu-v3
>> reg:
>> maxItems: 1
>> @@ -58,6 +63,15 @@ properties:
>> msi-parent: true
>> + nvidia,cmdqv:
>> + description: |
>> + A phandle to its pairing CMDQV extension for an implementation
>> on NVIDIA
>> + Tegra SoC.
>> +
>> + If this property is absent, CMDQ-Virtualization won't be used
>> and SMMU
>> + will only use its own CMDQ.
>> + $ref: /schemas/types.yaml#/definitions/phandle
>> +
>> hisilicon,broken-prefetch-cmd:
>> type: boolean
>> description: Avoid sending CMD_PREFETCH_* commands to the SMMU.
>> @@ -69,6 +83,17 @@ properties:
>> register access with page 0 offsets. Set for Cavium ThunderX2
>> silicon that
>> doesn't support SMMU page1 register space.
>> +allOf:
>> + - if:
>> + not:
>> + properties:
>> + compatible:
>> + contains:
>> + const: nvidia,tegra264-smmu
>> + then:
>> + properties:
>> + nvidia,cmdqv: false
>> +
>> required:
>> - compatible
>> - reg
>> @@ -82,7 +107,7 @@ examples:
>> #include <dt-bindings/interrupt-controller/irq.h>
>> iommu@...00000 {
>> - compatible = "arm,smmu-v3";
>> + compatible = "nvidia,tegra264-smmu", "arm,smmu-v3";
>> reg = <0x2b400000 0x20000>;
>> interrupts = <GIC_SPI 74 IRQ_TYPE_EDGE_RISING>,
>> <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>,
>> @@ -92,4 +117,5 @@ examples:
>> dma-coherent;
>> #iommu-cells = <1>;
>> msi-parent = <&its 0xff0000>;
>> + nvidia,cmdqv = <&cmdqv>;
>
> So I believe that this is a generic example for arm,smmu-v3, and so I
> am not sure we want to be adding all these NVIDIA specific bits here.
> What would be more appropriate is to add another example under the
> existing example specifically for Tegra264.
>
> Jon
>
Yeah, makes sense. However, I checked arm-smmu.yaml (v2) binding docs
and we had separate Nvidia specific compatible and property
(nvidia,memory-controller) there as well. But we didn't have a separate
example for showing this compatible and property. So, I wonder if we
even need to update the generic smmuv3 example for cmdqv property or
add a new example?
Can you all please share your inputs on this?
If required, I'll update the patch will the change below:
diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml
b/Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml
index 1c03482e4c61..6b07ca9928a7 100644
--- a/Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml
+++ b/Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml
@@ -107,7 +107,7 @@ examples:
#include <dt-bindings/interrupt-controller/irq.h>
iommu@...00000 {
- compatible = "nvidia,tegra264-smmu", "arm,smmu-v3";
+ compatible = "arm,smmu-v3";
reg = <0x2b400000 0x20000>;
interrupts = <GIC_SPI 74 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 75 IRQ_TYPE_EDGE_RISING>,
@@ -117,5 +117,26 @@ examples:
dma-coherent;
#iommu-cells = <1>;
msi-parent = <&its 0xff0000>;
+ };
+
+ - |+
+ /* Example for NVIDIA Tegra264 with CMDQV extension */
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/interrupt-controller/irq.h>
+
+ iommu@...0000 {
+ compatible = "nvidia,tegra264-smmu", "arm,smmu-v3";
+ reg = <0x5000000 0x200000>;
+ interrupts = <GIC_SPI 12 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 13 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "eventq", "gerror";
+ dma-coherent;
+ #iommu-cells = <1>;
nvidia,cmdqv = <&cmdqv>;
};
+
+ cmdqv: cmdqv@...0000 {
+ compatible = "nvidia,tegra264-cmdqv";
+ reg = <0x5200000 0x830000>;
+ interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
+ };
Thanks,
Ashish Mhetre
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