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Message-ID: <325a9641-a3cb-4137-8cca-99597ca2caa0@nvidia.com>
Date: Wed, 17 Dec 2025 20:42:31 +0000
From: Jon Hunter <jonathanh@...dia.com>
To: Ashish Mhetre <amhetre@...dia.com>, will@...nel.org,
robin.murphy@....com, joro@...tes.org, robh@...nel.org, krzk+dt@...nel.org,
conor+dt@...nel.org, nicolinc@...dia.com
Cc: thierry.reding@...il.com, vdumpa@...dia.com, jgg@...pe.ca,
linux-arm-kernel@...ts.infradead.org, iommu@...ts.linux.dev,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
linux-tegra@...r.kernel.org
Subject: Re: [PATCH V7 4/4] arm64: dts: nvidia: Add nodes for CMDQV
On 15/12/2025 06:48, Ashish Mhetre wrote:
> The Command Queue Virtualization (CMDQV) hardware is part of the
> SMMUv3 implementation on NVIDIA Tegra SoCs. It assists in
> virtualizing the command queue for the SMMU.
>
> Update SMMU compatible strings to use nvidia,tegra264-smmu to enable
> CMDQV support. Add device tree nodes for the CMDQV hardware and enable
> them on the tegra264-p3834 platform where SMMUs are enabled. Each SMMU
> instance is paired with its corresponding CMDQV instance via the
> nvidia,cmdqv property.
>
> Signed-off-by: Ashish Mhetre <amhetre@...dia.com>
> ---
> .../arm64/boot/dts/nvidia/tegra264-p3834.dtsi | 8 +++
> arch/arm64/boot/dts/nvidia/tegra264.dtsi | 50 +++++++++++++++++--
> 2 files changed, 53 insertions(+), 5 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/nvidia/tegra264-p3834.dtsi b/arch/arm64/boot/dts/nvidia/tegra264-p3834.dtsi
> index 06795c82427a..7e2c3e66c2ab 100644
> --- a/arch/arm64/boot/dts/nvidia/tegra264-p3834.dtsi
> +++ b/arch/arm64/boot/dts/nvidia/tegra264-p3834.dtsi
> @@ -23,8 +23,16 @@ iommu@...0000 {
> status = "okay";
> };
>
> + cmdqv@...0000 {
> + status = "okay";
> + };
> +
> iommu@...0000 {
> status = "okay";
> };
> +
> + cmdqv@...0000 {
> + status = "okay";
> + };
> };
> };
> diff --git a/arch/arm64/boot/dts/nvidia/tegra264.dtsi b/arch/arm64/boot/dts/nvidia/tegra264.dtsi
> index f137565da804..9eb7058e3149 100644
> --- a/arch/arm64/boot/dts/nvidia/tegra264.dtsi
> +++ b/arch/arm64/boot/dts/nvidia/tegra264.dtsi
> @@ -3361,7 +3361,7 @@ bus@...0000000 {
> <0x02 0x00000000 0xd0 0x00000000 0x08 0x80000000>; /* ECAM, prefetchable memory, I/O */
>
> smmu1: iommu@...0000 {
> - compatible = "arm,smmu-v3";
> + compatible = "nvidia,tegra264-smmu", "arm,smmu-v3";
> reg = <0x00 0x5000000 0x0 0x200000>;
> interrupts = <GIC_SPI 12 IRQ_TYPE_EDGE_RISING>,
> <GIC_SPI 13 IRQ_TYPE_EDGE_RISING>;
> @@ -3370,10 +3370,18 @@ smmu1: iommu@...0000 {
>
> #iommu-cells = <1>;
> dma-coherent;
> + nvidia,cmdqv = <&cmdqv1>;
> + };
> +
> + cmdqv1: cmdqv@...0000 {
> + compatible = "nvidia,tegra264-cmdqv";
> + reg = <0x00 0x5200000 0x0 0x830000>;
> + interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
> + status = "disabled";
> };
>
> smmu2: iommu@...0000 {
> - compatible = "arm,smmu-v3";
> + compatible = "nvidia,tegra264-smmu", "arm,smmu-v3";
> reg = <0x00 0x6000000 0x0 0x200000>;
> interrupts = <GIC_SPI 1 IRQ_TYPE_EDGE_RISING>,
> <GIC_SPI 2 IRQ_TYPE_EDGE_RISING>;
> @@ -3382,6 +3390,14 @@ smmu2: iommu@...0000 {
>
> #iommu-cells = <1>;
> dma-coherent;
> + nvidia,cmdqv = <&cmdqv2>;
> + };
> +
> + cmdqv2: cmdqv@...0000 {
> + compatible = "nvidia,tegra264-cmdqv";
> + reg = <0x00 0x6200000 0x0 0x830000>;
> + interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
> + status = "disabled";
> };
>
> mc: memory-controller@...0000 {
> @@ -3437,7 +3453,7 @@ emc: external-memory-controller@...0000 {
> };
>
> smmu0: iommu@...0000 {
> - compatible = "arm,smmu-v3";
> + compatible = "nvidia,tegra264-smmu", "arm,smmu-v3";
> reg = <0x00 0xa000000 0x0 0x200000>;
> interrupts = <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>,
> <GIC_SPI 22 IRQ_TYPE_EDGE_RISING>;
> @@ -3446,10 +3462,18 @@ smmu0: iommu@...0000 {
>
> #iommu-cells = <1>;
> dma-coherent;
> + nvidia,cmdqv = <&cmdqv0>;
> + };
> +
> + cmdqv0: cmdqv@...0000 {
> + compatible = "nvidia,tegra264-cmdqv";
> + reg = <0x00 0xa200000 0x0 0x830000>;
> + interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
> + status = "disabled";
> };
>
> smmu4: iommu@...0000 {
> - compatible = "arm,smmu-v3";
> + compatible = "nvidia,tegra264-smmu", "arm,smmu-v3";
> reg = <0x00 0xb000000 0x0 0x200000>;
> interrupts = <GIC_SPI 30 IRQ_TYPE_EDGE_RISING>,
> <GIC_SPI 31 IRQ_TYPE_EDGE_RISING>;
> @@ -3458,6 +3482,14 @@ smmu4: iommu@...0000 {
>
> #iommu-cells = <1>;
> dma-coherent;
> + nvidia,cmdqv = <&cmdqv4>;
> + };
> +
> + cmdqv4: cmdqv@...0000 {
> + compatible = "nvidia,tegra264-cmdqv";
> + reg = <0x00 0xb200000 0x0 0x830000>;
> + interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
> + status = "disabled";
> };
>
> i2c14: i2c@...0000 {
> @@ -3690,7 +3722,7 @@ bus@...0000000 {
> ranges = <0x00 0x00000000 0x88 0x00000000 0x01 0x00000000>;
>
> smmu3: iommu@...0000 {
> - compatible = "arm,smmu-v3";
> + compatible = "nvidia,tegra264-smmu", "arm,smmu-v3";
> reg = <0x00 0x6000000 0x0 0x200000>;
> interrupts = <GIC_SPI 225 IRQ_TYPE_EDGE_RISING>,
> <GIC_SPI 226 IRQ_TYPE_EDGE_RISING>;
> @@ -3699,6 +3731,14 @@ smmu3: iommu@...0000 {
>
> #iommu-cells = <1>;
> dma-coherent;
> + nvidia,cmdqv = <&cmdqv3>;
> + };
> +
> + cmdqv3: cmdqv@...0000 {
> + compatible = "nvidia,tegra264-cmdqv";
> + reg = <0x00 0x6200000 0x0 0x830000>;
> + interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>;
> + status = "disabled";
> };
>
> hda@...0000 {
Looks good to me.
Reviewed-by: Jon Hunter <jonathanh@...dia.com>
Jon
--
nvpublic
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