linux-kernel - Re: [PATCH v8 5/8] dt-bindings: arm: add an interrupt property for Coresight CTCU

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Message-ID: <a9537dc9-c767-4909-8b1c-6e939ce4f3fc@kernel.org>
Date: Thu, 18 Dec 2025 11:17:57 +0100
From: Krzysztof Kozlowski <krzk@...nel.org>
To: Jie Gan <jie.gan@....qualcomm.com>, Rob Herring <robh@...nel.org>
Cc: Suzuki K Poulose <suzuki.poulose@....com>,
 Mike Leach <mike.leach@...aro.org>, James Clark <james.clark@...aro.org>,
 Alexander Shishkin <alexander.shishkin@...ux.intel.com>,
 Krzysztof Kozlowski <krzk+dt@...nel.org>, Conor Dooley
 <conor+dt@...nel.org>, Tingwei Zhang <tingwei.zhang@....qualcomm.com>,
 Mao Jinlong <jinlong.mao@....qualcomm.com>,
 Bjorn Andersson <andersson@...nel.org>,
 Konrad Dybcio <konradybcio@...nel.org>, coresight@...ts.linaro.org,
 linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org,
 linux-arm-msm@...r.kernel.org, devicetree@...r.kernel.org
Subject: Re: [PATCH v8 5/8] dt-bindings: arm: add an interrupt property for
 Coresight CTCU

On 12/12/2025 02:12, Jie Gan wrote:
> 
> 
> On 12/11/2025 9:37 PM, Rob Herring wrote:
>> On Thu, Dec 11, 2025 at 02:10:44PM +0800, Jie Gan wrote:
>>> Add an interrupt property to CTCU device. The interrupt will be triggered
>>> when the data size in the ETR buffer exceeds the threshold of the
>>> BYTECNTRVAL register. Programming a threshold in the BYTECNTRVAL register
>>> of CTCU device will enable the interrupt.
>>>
>>> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>
>>> Reviewed-by: Mike Leach <mike.leach@...aro.org>
>>> Signed-off-by: Jie Gan <jie.gan@....qualcomm.com>
>>> ---
>>>   .../devicetree/bindings/arm/qcom,coresight-ctcu.yaml    | 17 +++++++++++++++++
>>>   1 file changed, 17 insertions(+)
>>>
>>> diff --git a/Documentation/devicetree/bindings/arm/qcom,coresight-ctcu.yaml b/Documentation/devicetree/bindings/arm/qcom,coresight-ctcu.yaml
>>> index c969c16c21ef..90f88cc6cd3e 100644
>>> --- a/Documentation/devicetree/bindings/arm/qcom,coresight-ctcu.yaml
>>> +++ b/Documentation/devicetree/bindings/arm/qcom,coresight-ctcu.yaml
>>> @@ -39,6 +39,16 @@ properties:
>>>       items:
>>>         - const: apb
>>>   
>>> +  interrupts:
>>> +    items:
>>> +      - description: Byte cntr interrupt for the first etr device
>>> +      - description: Byte cntr interrupt for the second etr device
>>> +
>>> +  interrupt-names:
>>> +    items:
>>> +      - const: etrirq0
>>> +      - const: etrirq1
>>
>> Names are kind of pointless when it is just foo<index>.
> 
> Hi Rob,
> 
> I was naming them as etr0/etr1. Are these names acceptable?

Obviously irq is redundant, but how does etr0 solves the problem of
calling it foo0?

I don't think you really read Rob's comment.

> The interrupts are assigned exclusively to a specific ETR device.
> 
> But Suzuki is concerned that this might cause confusion because the ETR 
> device is named randomly in the driver. Suzuki suggested using ‘port-0’ 
> and ‘port-1’ and would also like to hear your feedback on these names.

There is no confusion here. Writing bindings luckily clarifies this what
the indices in the array mean.

> 
> Usually, the probe sequence follows the order of the addresses. In our 
> specification, ‘ETR0’ is always probed before ‘ETR1’ because its address 
> is lower.

How is this even relevant? You are answering to something completely
different, so I don't think you really tried to understand review.



Best regards,
Krzysztof