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Message-Id: <20251219-milos-mdss-v1-4-4537a916bdf9@fairphone.com>
Date: Fri, 19 Dec 2025 17:41:10 +0100
From: Luca Weiss <luca.weiss@...rphone.com>
To: Bjorn Andersson <andersson@...nel.org>,
Konrad Dybcio <konradybcio@...nel.org>,
Rob Clark <robin.clark@....qualcomm.com>,
Dmitry Baryshkov <lumag@...nel.org>,
Abhinav Kumar <abhinav.kumar@...ux.dev>,
Jessica Zhang <jessica.zhang@....qualcomm.com>, Sean Paul <sean@...rly.run>,
Marijn Suijten <marijn.suijten@...ainline.org>,
David Airlie <airlied@...il.com>, Simona Vetter <simona@...ll.ch>,
Rob Herring <robh@...nel.org>, Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>
Cc: ~postmarketos/upstreaming@...ts.sr.ht, phone-devel@...r.kernel.org,
linux-arm-msm@...r.kernel.org, linux-kernel@...r.kernel.org,
dri-devel@...ts.freedesktop.org, freedreno@...ts.freedesktop.org,
devicetree@...r.kernel.org, Luca Weiss <luca.weiss@...rphone.com>
Subject: [PATCH RFC 4/6] drm/msm/dpu: Add Milos support
Add definitions for the display hardware used on the Qualcomm Milos
platform.
Signed-off-by: Luca Weiss <luca.weiss@...rphone.com>
---
.../gpu/drm/msm/disp/dpu1/catalog/dpu_10_2_milos.h | 284 +++++++++++++++++++++
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 22 ++
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 1 +
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 1 +
4 files changed, 308 insertions(+)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_2_milos.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_2_milos.h
new file mode 100644
index 000000000000..75deec923897
--- /dev/null
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_2_milos.h
@@ -0,0 +1,284 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2022. Qualcomm Innovation Center, Inc. All rights reserved.
+ * Copyright (c) 2015-2018, 2020 The Linux Foundation. All rights reserved.
+ * Copyright (c) 2025, Luca Weiss <luca.weiss@...rphone.com>
+ */
+
+#ifndef _DPU_10_2_MILOS_H
+#define _DPU_10_2_MILOS_H
+
+static const struct dpu_caps milos_dpu_caps = {
+ .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH, // OK
+ .max_mixer_blendstages = 0x7, // OK
+ .has_src_split = true, // OK
+ .has_dim_layer = true, // OK
+ .has_idle_pc = true, // OK?
+ .has_3d_merge = true, // OK?
+ .max_linewidth = 8192, // OK
+ .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE, // OK
+};
+
+static const struct dpu_mdp_cfg milos_mdp = {
+ .name = "top_0",
+ .base = 0, .len = 0x494, // TODO? maybe qcom,sde-len = <0x488>;
+ .clk_ctrls = {
+ [DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 }, // OK
+ },
+};
+
+static const struct dpu_ctl_cfg milos_ctl[] = { // number of ctl is okay, base probably also
+ {
+ .name = "ctl_0", .id = CTL_0,
+ .base = 0x15000, .len = 0x1000,
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9), // FIXME?
+ }, {
+ .name = "ctl_1", .id = CTL_1,
+ .base = 0x16000, .len = 0x1000,
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
+ }, {
+ .name = "ctl_2", .id = CTL_2,
+ .base = 0x17000, .len = 0x1000,
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
+ }, {
+ .name = "ctl_3", .id = CTL_3,
+ .base = 0x18000, .len = 0x1000,
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
+ },
+};
+
+static const struct dpu_sspp_cfg milos_sspp[] = {
+ {
+ .name = "sspp_0", .id = SSPP_VIG0, // OK
+ .base = 0x4000, .len = 0x344, // OK
+ .features = VIG_SDM845_MASK_SDMA, // TODO?
+ .sblk = &dpu_vig_sblk_qseed3_3_3, // TODO?
+ .xin_id = 0, // OK
+ .type = SSPP_TYPE_VIG, // OK
+ }, {
+ .name = "sspp_8", .id = SSPP_DMA0, // FIXME name?
+ .base = 0x24000, .len = 0x344,
+ .features = DMA_SDM845_MASK_SDMA,
+ .sblk = &dpu_dma_sblk,
+ .xin_id = 1, // OK
+ .type = SSPP_TYPE_DMA, // OK
+ }, {
+ .name = "sspp_9", .id = SSPP_DMA1,
+ .base = 0x26000, .len = 0x344,
+ .features = DMA_SDM845_MASK_SDMA,
+ .sblk = &dpu_dma_sblk,
+ .xin_id = 5, // OK
+ .type = SSPP_TYPE_DMA, // OK
+ }, {
+ .name = "sspp_10", .id = SSPP_DMA2,
+ .base = 0x28000, .len = 0x344,
+ .features = DMA_SDM845_MASK_SDMA,
+ .sblk = &dpu_dma_sblk,
+ .xin_id = 9, // OK
+ .type = SSPP_TYPE_DMA, // OK
+ },
+};
+
+static const struct dpu_lm_cfg milos_lm[] = {
+ {
+ .name = "lm_0", .id = LM_0, // OK
+ .base = 0x44000, .len = 0x400,// OK
+ .features = MIXER_MSM8998_MASK, // TODO
+ .sblk = &sdm845_lm_sblk, // OK
+ .pingpong = PINGPONG_0, // TODO
+ .dspp = DSPP_0, // TODO
+ }, {
+ .name = "lm_2", .id = LM_2,
+ .base = 0x46000, .len = 0x400,
+ .features = MIXER_MSM8998_MASK,
+ .sblk = &sdm845_lm_sblk, // OK
+ .lm_pair = LM_3, // OK
+ .pingpong = PINGPONG_2,
+ //.dspp = DSPP_2, // FIXME?
+ }, {
+ .name = "lm_3", .id = LM_3,
+ .base = 0x47000, .len = 0x400,
+ .features = MIXER_MSM8998_MASK,
+ .sblk = &sdm845_lm_sblk, // OK
+ .lm_pair = LM_2, // OK
+ .pingpong = PINGPONG_3,
+ //.dspp = DSPP_3, // FIXME?
+ },
+};
+
+static const struct dpu_dspp_cfg milos_dspp[] = {
+ {
+ .name = "dspp_0", .id = DSPP_0, // OK
+ .base = 0x54000, .len = 0x1800, // OK
+ .sblk = &sdm845_dspp_sblk, // TODO
+ },
+};
+
+static const struct dpu_pingpong_cfg milos_pp[] = {
+ {
+ .name = "pingpong_0", .id = PINGPONG_0, // OK
+ .base = 0x69000, .len = 0, // OK
+ .sblk = &sc7280_pp_sblk, // OK
+ .merge_3d = MERGE_3D_0, // OK
+ .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), // TODO
+ }, {
+ .name = "pingpong_2", .id = PINGPONG_2, // TODO
+ .base = 0x6b000, .len = 0, // OK
+ .sblk = &sc7280_pp_sblk, // OK
+ .merge_3d = MERGE_3D_1, // OK
+ .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10),
+ }, {
+ .name = "pingpong_3", .id = PINGPONG_3,
+ .base = 0x6c000, .len = 0, // OK
+ .sblk = &sc7280_pp_sblk, // OK
+ .merge_3d = MERGE_3D_1, // OK
+ .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11),
+ }, {
+ .name = "pingpong_cwb_0", .id = PINGPONG_CWB_0,
+ .base = 0x66000, .len = 0, // OK
+ .sblk = &sc7280_pp_sblk, // OK
+ },
+};
+
+static const struct dpu_merge_3d_cfg milos_merge_3d[] = {
+ {
+ .name = "merge_3d_1", .id = MERGE_3D_1, // TODO
+ .base = 0x4f000, .len = 0x8,
+ },
+};
+
+/*
+ * NOTE: Each display compression engine (DCE) contains dual hard
+ * slice DSC encoders so both share same base address but with
+ * its own different sub block address.
+ */
+static const struct dpu_dsc_cfg milos_dsc[] = {
+ {
+ .name = "dce_0_0", .id = DSC_0, // OK
+ .base = 0x80000, .len = 0x6, // OK
+ .features = BIT(DPU_DSC_NATIVE_42x_EN), // TODO
+ .sblk = &dsc_sblk_0, // TODO
+ }, {
+ .name = "dce_0_1", .id = DSC_1, // OK
+ .base = 0x80000, .len = 0x6, // OK
+ .features = BIT(DPU_DSC_NATIVE_42x_EN), // TODO
+ .sblk = &dsc_sblk_1, // TODO
+ },
+};
+
+static const struct dpu_wb_cfg milos_wb[] = {
+ {
+ .name = "wb_2", .id = WB_2, // TODO
+ .base = 0x65000, .len = 0x2c8, // OK
+ .features = WB_SDM845_MASK, // TODO
+ .format_list = wb2_formats_rgb_yuv, // TODO
+ .num_formats = ARRAY_SIZE(wb2_formats_rgb_yuv), // TODO
+ .xin_id = 6, // OK
+ .vbif_idx = VBIF_RT, // TODO
+ .maxlinewidth = 4096, // OK
+ .intr_wb_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 4), // TODO
+ },
+};
+
+static const struct dpu_cwb_cfg milos_cwb[] = {
+ {
+ .name = "cwb_0", .id = CWB_0,
+ .base = 0x66200, .len = 0x8,
+ },
+};
+
+static const struct dpu_intf_cfg milos_intf[] = {
+ {
+ .name = "intf_0", .id = INTF_0, // OK
+ .base = 0x34000, .len = 0x280, // OK size=0x300?
+ .type = INTF_DP, // OK
+ .controller_id = MSM_DP_CONTROLLER_0, // OK?
+ .prog_fetch_lines_worst_case = 24, // TODO
+ .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24), // TODO
+ .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25), // TODO
+ }, {
+ .name = "intf_1", .id = INTF_1, // OK
+ .base = 0x35000, .len = 0x300, // OK size=0x300?
+ .type = INTF_DSI, // OK
+ .controller_id = MSM_DSI_CONTROLLER_0, // OK?
+ .prog_fetch_lines_worst_case = 24, // TODO
+ .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26), // TODO
+ .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27), // TODO
+ .intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2), // TODO
+ }, {
+ .name = "intf_3", .id = INTF_3, // TODO?
+ .base = 0x37000, .len = 0x280, // OK size=0x300?
+ .type = INTF_DP, // OK
+ .controller_id = MSM_DP_CONTROLLER_1, // FIXME, only one DP controller?
+ .prog_fetch_lines_worst_case = 24, // TODO
+ .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30), // TODO
+ .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31), // TODO
+ },
+};
+
+static const struct dpu_perf_cfg milos_perf_data = {
+ .max_bw_low = 7100000,
+ .max_bw_high = 9800000,
+ .min_core_ib = 2500000,
+ .min_llcc_ib = 0,
+ .min_dram_ib = 1600000,
+ .min_prefill_lines = 35, // TODO
+ /* FIXME: lut tables */
+ .danger_lut_tbl = {0x3ffff, 0x3ffff, 0x0}, // TODO
+ .safe_lut_tbl = {0xfe00, 0xfe00, 0xffff}, // TODO
+ .qos_lut_tbl = { // TODO
+ {.nentry = ARRAY_SIZE(sc7180_qos_linear),
+ .entries = sc7180_qos_linear
+ },
+ {.nentry = ARRAY_SIZE(sc7180_qos_macrotile),
+ .entries = sc7180_qos_macrotile
+ },
+ {.nentry = ARRAY_SIZE(sc7180_qos_nrt),
+ .entries = sc7180_qos_nrt
+ },
+ /* TODO: macrotile-qseed is different from macrotile */
+ },
+ .cdp_cfg = { // TODO
+ {.rd_enable = 1, .wr_enable = 1},
+ {.rd_enable = 1, .wr_enable = 0}
+ },
+ .clk_inefficiency_factor = 105, // TODO
+ .bw_inefficiency_factor = 120, // TODO
+};
+
+static const struct dpu_mdss_version milos_mdss_ver = {
+ .core_major_ver = 10,
+ .core_minor_ver = 2,
+};
+
+const struct dpu_mdss_cfg dpu_milos_cfg = {
+ .mdss_ver = &milos_mdss_ver,
+ .caps = &milos_dpu_caps,
+ .mdp = &milos_mdp,
+ .cdm = &dpu_cdm_5_x,
+ .ctl_count = ARRAY_SIZE(milos_ctl),
+ .ctl = milos_ctl,
+ .sspp_count = ARRAY_SIZE(milos_sspp),
+ .sspp = milos_sspp,
+ .mixer_count = ARRAY_SIZE(milos_lm),
+ .mixer = milos_lm,
+ .dspp_count = ARRAY_SIZE(milos_dspp),
+ .dspp = milos_dspp,
+ .pingpong_count = ARRAY_SIZE(milos_pp),
+ .pingpong = milos_pp,
+ .dsc_count = ARRAY_SIZE(milos_dsc),
+ .dsc = milos_dsc,
+ .merge_3d_count = ARRAY_SIZE(milos_merge_3d),
+ .merge_3d = milos_merge_3d,
+ .wb_count = ARRAY_SIZE(milos_wb),
+ .wb = milos_wb,
+ .cwb_count = ARRAY_SIZE(milos_cwb),
+ .cwb = milos_cwb,
+ .intf_count = ARRAY_SIZE(milos_intf),
+ .intf = milos_intf,
+ .vbif_count = ARRAY_SIZE(milos_vbif),
+ .vbif = milos_vbif,
+ .perf = &milos_perf_data,
+};
+
+#endif
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
index 9f8d1bba9139..4d5b57d6295f 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
@@ -555,6 +555,26 @@ static const struct dpu_vbif_cfg sdm845_vbif[] = {
},
};
+static const struct dpu_vbif_cfg milos_vbif[] = {
+ {
+ .name = "vbif_rt", .id = VBIF_RT, // OK
+ .base = 0, .len = 0x1074, // OK
+ .features = BIT(DPU_VBIF_QOS_REMAP), // TODO
+ .xin_halt_timeout = 0x4000, // TODO
+ .qos_rp_remap_size = 0x40, // TODO
+ .qos_rt_tbl = { // TODO
+ .npriority_lvl = ARRAY_SIZE(sm8650_rt_pri_lvl),
+ .priority_lvl = sm8650_rt_pri_lvl,
+ },
+ .qos_nrt_tbl = { // TODO
+ .npriority_lvl = ARRAY_SIZE(sdm845_nrt_pri_lvl),
+ .priority_lvl = sdm845_nrt_pri_lvl,
+ },
+ .memtype_count = 16, // OK
+ .memtype = {3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3}, // OK?
+ },
+};
+
static const struct dpu_vbif_cfg sm8550_vbif[] = {
{
.name = "vbif_rt", .id = VBIF_RT,
@@ -725,4 +745,6 @@ static const struct dpu_qos_lut_entry sc7180_qos_nrt[] = {
#include "catalog/dpu_9_2_x1e80100.h"
#include "catalog/dpu_10_0_sm8650.h"
+#include "catalog/dpu_10_2_milos.h"
+
#include "catalog/dpu_12_0_sm8750.h"
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
index f0768f54e9b3..1f6b14f1c4d6 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
@@ -749,6 +749,7 @@ struct dpu_mdss_cfg {
const struct dpu_format_extended *vig_formats;
};
+extern const struct dpu_mdss_cfg dpu_milos_cfg;
extern const struct dpu_mdss_cfg dpu_msm8917_cfg;
extern const struct dpu_mdss_cfg dpu_msm8937_cfg;
extern const struct dpu_mdss_cfg dpu_msm8953_cfg;
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
index 4e5a8ecd31f7..7afd7dc7a0b4 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
@@ -1505,6 +1505,7 @@ static const struct dev_pm_ops dpu_pm_ops = {
};
static const struct of_device_id dpu_dt_match[] = {
+ { .compatible = "qcom,milos-dpu", .data = &dpu_milos_cfg, },
{ .compatible = "qcom,msm8917-mdp5", .data = &dpu_msm8917_cfg, },
{ .compatible = "qcom,msm8937-mdp5", .data = &dpu_msm8937_cfg, },
{ .compatible = "qcom,msm8953-mdp5", .data = &dpu_msm8953_cfg, },
--
2.52.0
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