linux-kernel - Re: [PATCH v2 2/2] PCI: rzg3s-host: Drop the lock on RZG3S_PCI_MSIRS and RZG3S_PCI

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Message-ID: <aUZdQdXNDdZka-JU@shikoro>
Date: Sat, 20 Dec 2025 09:24:33 +0100
From: Wolfram Sang <wsa+renesas@...g-engineering.com>
To: Claudiu <claudiu.beznea@...on.dev>
Cc: bhelgaas@...gle.com, lpieralisi@...nel.org, kwilczynski@...nel.org,
	mani@...nel.org, robh@...nel.org, linux-pci@...r.kernel.org,
	linux-renesas-soc@...r.kernel.org, linux-kernel@...r.kernel.org,
	Claudiu Beznea <claudiu.beznea.uj@...renesas.com>
Subject: Re: [PATCH v2 2/2] PCI: rzg3s-host: Drop the lock on RZG3S_PCI_MSIRS
 and RZG3S_PCI_PINTRCVIS

On Wed, Dec 17, 2025 at 01:15:10PM +0200, Claudiu wrote:
> From: Claudiu Beznea <claudiu.beznea.uj@...renesas.com>
> 
> The RZG3S_PCI_MSIRS and RZG3S_PCI_PINTRCVIS registers are of the R/W1C
> type. According to the RZ/G3S HW Manual, Rev. 1.10, chapter 34.2.1
> Register Type, R/W1C register bits are cleared to 0b by writing 1b, while
> writing 0b has no effect. Therefore, there is no need to take a lock
> around writes to these registers.
> 
> Drop the locking.
> 
> Along with this, add a note about the R/W1C register type to the register
> offset definitions.
> 
> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@...renesas.com>

Tested-by: Wolfram Sang <wsa+renesas@...g-engineering.com>


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