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Message-ID: <k5b7rixvjtfxwatsg7ahmrutcruuxa4rxecprnbni3kvtfbcuo@26falgq6n24s>
Date: Sat, 20 Dec 2025 20:46:31 +0200
From: Dmitry Baryshkov <dmitry.baryshkov@....qualcomm.com>
To: Pankaj Patil <pankaj.patil@....qualcomm.com>
Cc: Bjorn Andersson <andersson@...nel.org>,
Konrad Dybcio <konradybcio@...nel.org>, Rob Herring <robh@...nel.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>, linux-arm-msm@...r.kernel.org,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
rajendra.nayak@....qualcomm.com, sibi.sankar@....qualcomm.com,
Jyothi Kumar Seerapu <jyothi.seerapu@....qualcomm.com>,
Maulik Shah <maulik.shah@....qualcomm.com>,
Taniya Das <taniya.das@....qualcomm.com>,
Kamal Wadhwa <kamal.wadhwa@....qualcomm.com>,
Prudhvi Yarlagadda <quic_pyarlaga@...cinc.com>,
Qiang Yu <qiang.yu@....qualcomm.com>,
Manaf Meethalavalappu Pallikunhi <manaf.pallikunhi@....qualcomm.com>,
Jishnu Prakash <jishnu.prakash@....qualcomm.com>,
Abel Vesa <abelvesa@...nel.org>
Subject: Re: [PATCH v3 3/4] arm64: dts: qcom: Introduce Glymur base dtsi
On Fri, Dec 19, 2025 at 08:16:56PM +0530, Pankaj Patil wrote:
> Introduce the base device tree support for Glymur – Qualcomm's
> next-generation compute SoC. The new glymur.dtsi describes the core SoC
> components, including:
>
> - CPUs and CPU topology
> - Interrupt controller and TLMM
> - GCC,DISPCC and RPMHCC clock controllers
> - Reserved memory and interconnects
> - SMMU and firmware SCM
> - Watchdog, RPMHPD, APPS RSC and SRAM
> - PSCI and PMU nodes
> - QUPv3 serial engines
> - CPU power domains and idle states, plus SCMI/ SRAM pieces for CPU DVFS
> - PDP0 mailbox, IPCC and AOSS
> - Display clock controller
> - SPMI PMIC arbiter with SPMI0/1/2 buses
> - SMP2P nodes
> - TSENS and thermal zones (8 instances, 92 sensors)
>
> Add dtsi files for PMH0101, PMK8850, PMCX0102, SMB2370, PMH0104,
> PMH0110 along with temp-alarm and GPIO nodes needed on Glymur
>
> Add glmur-pmics.dtsi file for all the pmics enabled
>
> Enabled PCIe controllers and associated PHY to support boot to
> shell with nvme storage,
> List of PCIe instances enabled:
>
> - PCIe3b
> - PCIe4
> - PCIe5
> - PCIe6
>
> Co-developed-by: Jyothi Kumar Seerapu <jyothi.seerapu@....qualcomm.com>
> Signed-off-by: Jyothi Kumar Seerapu <jyothi.seerapu@....qualcomm.com>
> Co-developed-by: Maulik Shah <maulik.shah@....qualcomm.com>
> Signed-off-by: Maulik Shah <maulik.shah@....qualcomm.com>
> Co-developed-by: Sibi Sankar <sibi.sankar@....qualcomm.com>
> Signed-off-by: Sibi Sankar <sibi.sankar@....qualcomm.com>
> Co-developed-by: Taniya Das <taniya.das@....qualcomm.com>
> Signed-off-by: Taniya Das <taniya.das@....qualcomm.com>
> Co-developed-by: Kamal Wadhwa <kamal.wadhwa@....qualcomm.com>
> Signed-off-by: Kamal Wadhwa <kamal.wadhwa@....qualcomm.com>
> Co-developed-by: Prudhvi Yarlagadda <quic_pyarlaga@...cinc.com>
> Signed-off-by: Prudhvi Yarlagadda <quic_pyarlaga@...cinc.com>
> Co-developed-by: Qiang Yu <qiang.yu@....qualcomm.com>
> Signed-off-by: Qiang Yu <qiang.yu@....qualcomm.com>
> Co-developed-by: Abel Vesa <abel.vesa@...aro.org>
> Signed-off-by: Abel Vesa <abel.vesa@...aro.org>
> Co-developed-by: Manaf Meethalavalappu Pallikunhi <manaf.pallikunhi@....qualcomm.com>
> Signed-off-by: Manaf Meethalavalappu Pallikunhi <manaf.pallikunhi@....qualcomm.com>
> Co-developed-by: Jishnu Prakash <jishnu.prakash@....qualcomm.com>
> Signed-off-by: Jishnu Prakash <jishnu.prakash@....qualcomm.com>
> Signed-off-by: Pankaj Patil <pankaj.patil@....qualcomm.com>
> ---
> arch/arm64/boot/dts/qcom/glymur-pmics.dtsi | 11 +
> arch/arm64/boot/dts/qcom/glymur.dtsi | 5700 ++++++++++++++++++++++++++
> arch/arm64/boot/dts/qcom/pmcx0102.dtsi | 132 +
> arch/arm64/boot/dts/qcom/pmh0101.dtsi | 45 +
> arch/arm64/boot/dts/qcom/pmh0104-glymur.dtsi | 83 +
> arch/arm64/boot/dts/qcom/pmh0110-glymur.dtsi | 83 +
> arch/arm64/boot/dts/qcom/pmk8850.dtsi | 70 +
> arch/arm64/boot/dts/qcom/smb2370.dtsi | 45 +
> 8 files changed, 6169 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/glymur-pmics.dtsi b/arch/arm64/boot/dts/qcom/glymur-pmics.dtsi
> new file mode 100644
> index 000000000000..677dd1b74db0
> --- /dev/null
> +++ b/arch/arm64/boot/dts/qcom/glymur-pmics.dtsi
> @@ -0,0 +1,11 @@
> +// SPDX-License-Identifier: BSD-3-Clause
> +/*
> + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
> + */
> +
> +#include "pmk8850.dtsi" /* SPMI0: SID-0 */
> +#include "pmh0101.dtsi" /* SPMI0: SID-1 */
> +#include "pmcx0102.dtsi" /* SPMI0: SID-2/3 SPMI1: SID-2/3 */
> +#include "pmh0110-glymur.dtsi" /* SPMI0: SID-5/7 SPMI1: SID-5 */
> +#include "pmh0104-glymur.dtsi" /* SPMI0: SID-8/9 SPMI1: SID-11 */
> +#include "smb2370.dtsi" /* SPMI2: SID-9/10/11 */
> diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qcom/glymur.dtsi
> new file mode 100644
> index 000000000000..eb042541cfe1
> --- /dev/null
> +++ b/arch/arm64/boot/dts/qcom/glymur.dtsi
> @@ -0,0 +1,5700 @@
> +// SPDX-License-Identifier: BSD-3-Clause
> +/*
> + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
> + */
> +
> +#include <dt-bindings/clock/qcom,glymur-dispcc.h>
> +#include <dt-bindings/clock/qcom,glymur-gcc.h>
> +#include <dt-bindings/clock/qcom,glymur-tcsr.h>
> +#include <dt-bindings/clock/qcom,rpmh.h>
> +#include <dt-bindings/dma/qcom-gpi.h>
> +#include <dt-bindings/gpio/gpio.h>
> +#include <dt-bindings/interconnect/qcom,icc.h>
> +#include <dt-bindings/interconnect/qcom,glymur-rpmh.h>
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +#include <dt-bindings/mailbox/qcom-ipcc.h>
> +#include <dt-bindings/phy/phy-qcom-qmp.h>
> +#include <dt-bindings/power/qcom,rpmhpd.h>
> +#include <dt-bindings/power/qcom-rpmpd.h>
> +#include <dt-bindings/soc/qcom,rpmh-rsc.h>
> +#include <dt-bindings/spmi/spmi.h>
> +
> +#include "glymur-ipcc.h"
What is it and why is it being included this way?
> +
> +/ {
> + interrupt-parent = <&intc>;
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
> +
> + spi19: spi@...000 {
> + compatible = "qcom,geni-spi";
> + reg = <0x0 0x0088c000 0x0 0x4000>;
> + interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
> + clock-names = "se";
> + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
> + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
> + <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
> + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
> + <&aggre3_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
> + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
> + interconnect-names = "qup-core",
> + "qup-config",
> + "qup-memory";
> + dmas = <&gpi_dma2 0 3 QCOM_GPI_SPI>,
> + <&gpi_dma2 1 3 QCOM_GPI_SPI>;
> + dma-names = "tx",
> + "rx";
> + pinctrl-0 = <&qup_spi19_data_clk>, <&qup_spi19_cs>;
> + pinctrl-names = "default";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + status = "disabled";
> + };
> +
> + uart19: serial@...000 {
> + compatible = "qcom,geni-uart";
> + reg = <0x0 0x0088c000 0x0 0x4000>;
> + interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
> + clock-names = "se";
> + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
> + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
Here and further, please keep the entries aligned (as they were before)
> + <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
> + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
> + <&aggre3_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
> + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
> + interconnect-names = "qup-core",
> + "qup-config",
> + "qup-memory";
> + pinctrl-0 = <&qup_uart19_default>;
> + pinctrl-names = "default";
> + status = "disabled";
> + };
> +
> +
> + pcie4: pci@...0000 {
> + device_type = "pci";
> + compatible = "qcom,glymur-pcie", "qcom,pcie-x1e80100";
> + reg = <0x0 0x01bf0000 0x0 0x3000>,
> + <0x0 0x78000000 0x0 0xf20>,
> + <0x0 0x78000f40 0x0 0xa8>,
> + <0x0 0x78001000 0x0 0x4000>,
> + <0x0 0x78005000 0x0 0x100000>,
> + <0x0 0x01bf3000 0x0 0x1000>;
> + reg-names = "parf",
> + "dbi",
> + "elbi",
> + "atu",
> + "config",
> + "mhi";
> + #address-cells = <3>;
> + #size-cells = <2>;
> + ranges = <0x01000000 0x0 0x00000000 0x0 0x78105000 0x0 0x100000>,
> + <0x02000000 0x0 0x78205000 0x0 0x78205000 0x0 0x1dfb000>,
> + <0x03000000 0x7 0x80000000 0x7 0x80000000 0x0 0x20000000>;
Also not aligned
> + bus-range = <0 0xff>;
0x00 0xff
> +
> + dma-coherent;
> +
> + linux,pci-domain = <4>;
> + num-lanes = <2>;
> +
> + operating-points-v2 = <&pcie4_opp_table>;
> +
> + msi-map = <0x0 &gic_its 0xc0000 0x10000>;
> +
> + interrupts = <GIC_SPI 505 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 510 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 511 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 512 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 944 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "msi0",
> + "msi1",
> + "msi2",
> + "msi3",
> + "msi4",
> + "msi5",
> + "msi6",
> + "msi7",
> + "global";
> +
> + #interrupt-cells = <1>;
> + interrupt-map-mask = <0 0 0 0x7>;
> + interrupt-map = <0 0 0 1 &intc 0 0 0 513 IRQ_TYPE_LEVEL_HIGH>,
> + <0 0 0 2 &intc 0 0 0 514 IRQ_TYPE_LEVEL_HIGH>,
> + <0 0 0 3 &intc 0 0 0 515 IRQ_TYPE_LEVEL_HIGH>,
> + <0 0 0 4 &intc 0 0 0 516 IRQ_TYPE_LEVEL_HIGH>;
> +
> + clocks = <&gcc GCC_PCIE_4_AUX_CLK>,
> + <&gcc GCC_PCIE_4_CFG_AHB_CLK>,
> + <&gcc GCC_PCIE_4_MSTR_AXI_CLK>,
> + <&gcc GCC_PCIE_4_SLV_AXI_CLK>,
> + <&gcc GCC_PCIE_4_SLV_Q2A_AXI_CLK>,
> + <&gcc GCC_AGGRE_NOC_PCIE_4_WEST_SF_AXI_CLK>;
> + clock-names = "aux",
> + "cfg",
> + "bus_master",
> + "bus_slave",
> + "slave_q2a",
> + "noc_aggr";
> +
> + assigned-clocks = <&gcc GCC_PCIE_4_AUX_CLK>;
> + assigned-clock-rates = <19200000>;
> +
> + interconnects = <&pcie_west_anoc MASTER_PCIE_4 QCOM_ICC_TAG_ALWAYS
> + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
> + <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
> + &pcie_west_slv_noc SLAVE_PCIE_4 QCOM_ICC_TAG_ALWAYS>;
And here too
> + interconnect-names = "pcie-mem",
> + "cpu-pcie";
> +
> + resets = <&gcc GCC_PCIE_4_BCR>,
> + <&gcc GCC_PCIE_4_LINK_DOWN_BCR>;
> + reset-names = "pci",
> + "link_down";
> +
> + power-domains = <&gcc GCC_PCIE_4_GDSC>;
> +
> + eq-presets-8gts = /bits/ 16 <0x5555 0x5555>;
> + eq-presets-16gts = /bits/ 8 <0x55 0x55>;
> +
> + status = "disabled";
> +
> + pcie4_opp_table: opp-table {
> + compatible = "operating-points-v2";
> +
> + /* GEN 1 x1 */
> + opp-2500000 {
> + opp-hz = /bits/ 64 <2500000>;
> + required-opps = <&rpmhpd_opp_low_svs>;
> + opp-peak-kBps = <250000 1>;
> + };
> +
> + /* GEN 1 x2 and GEN 2 x1 */
> + opp-5000000 {
> + opp-hz = /bits/ 64 <5000000>;
> + required-opps = <&rpmhpd_opp_low_svs>;
> + opp-peak-kBps = <500000 1>;
> + };
> +
> + /* GEN 2 x2 */
> + opp-10000000 {
> + opp-hz = /bits/ 64 <10000000>;
> + required-opps = <&rpmhpd_opp_low_svs>;
> + opp-peak-kBps = <1000000 1>;
> + };
> +
> + /* GEN 3 x1 */
> + opp-8000000 {
> + opp-hz = /bits/ 64 <8000000>;
> + required-opps = <&rpmhpd_opp_low_svs>;
> + opp-peak-kBps = <984500 1>;
> + };
> +
> + /* GEN 3 x2 and GEN 4 x1 */
> + opp-16000000 {
> + opp-hz = /bits/ 64 <16000000>;
> + required-opps = <&rpmhpd_opp_low_svs>;
> + opp-peak-kBps = <1969000 1>;
> + };
> +
> + /* GEN 4 x2 */
> + opp-32000000 {
> + opp-hz = /bits/ 64 <32000000>;
> + required-opps = <&rpmhpd_opp_low_svs>;
> + opp-peak-kBps = <3938000 1>;
> + };
> +
> + };
> +
> + pcie4_port0: pcie@0 {
> + device_type = "pci";
> + reg = <0x0 0x0 0x0 0x0 0x0>;
> + bus-range = <0x01 0xff>;
> +
> + phys = <&pcie4_phy>;
> +
> + #address-cells = <3>;
> + #size-cells = <2>;
> + ranges;
> + };
> + };
> +
> + pcie4_phy: phy@...6000 {
> + compatible = "qcom,glymur-qmp-gen4x2-pcie-phy";
> + reg = <0x0 0x01bf6000 0x0 0x2000>;
> +
> + clocks = <&gcc GCC_PCIE_PHY_4_AUX_CLK>,
> + <&gcc GCC_PCIE_4_CFG_AHB_CLK>,
> + <&tcsr TCSR_PCIE_2_CLKREF_EN>,
> + <&gcc GCC_PCIE_4_PHY_RCHNG_CLK>,
> + <&gcc GCC_PCIE_4_PIPE_CLK>,
> + <&gcc GCC_PCIE_4_PIPE_DIV2_CLK>;
> + clock-names = "aux",
> + "cfg_ahb",
> + "ref",
> + "rchng",
> + "pipe",
> + "pipediv2";
You can guess
> +
> + resets = <&gcc GCC_PCIE_4_PHY_BCR>,
> + <&gcc GCC_PCIE_4_NOCSR_COM_PHY_BCR>;
> + reset-names = "phy",
> + "phy_nocsr";
> +
> + assigned-clocks = <&gcc GCC_PCIE_4_PHY_RCHNG_CLK>;
> + assigned-clock-rates = <100000000>;
> +
> + power-domains = <&gcc GCC_PCIE_4_PHY_GDSC>;
> +
> + #clock-cells = <0>;
> + clock-output-names = "pcie4_pipe_clk";
> +
> + #phy-cells = <0>;
> +
> + status = "disabled";
> + };
> +
--
With best wishes
Dmitry
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