linux-kernel - Re: [PATCH v3 3/4] arm64: dts: qcom: Introduce Glymur base dtsi

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Message-ID: <6wwgg44t5ocakherrqjnzb4tx6tus4mitrwfkbu66o57ogzuaa@g6ghhl6zkfn3>
Date: Sun, 21 Dec 2025 04:49:33 +0200
From: Dmitry Baryshkov <dmitry.baryshkov@....qualcomm.com>
To: Pankaj Patil <pankaj.patil@....qualcomm.com>
Cc: Bjorn Andersson <andersson@...nel.org>,
        Konrad Dybcio <konradybcio@...nel.org>, Rob Herring <robh@...nel.org>,
        Krzysztof Kozlowski <krzk+dt@...nel.org>,
        Conor Dooley <conor+dt@...nel.org>, linux-arm-msm@...r.kernel.org,
        devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
        rajendra.nayak@....qualcomm.com, sibi.sankar@....qualcomm.com,
        Jyothi Kumar Seerapu <jyothi.seerapu@....qualcomm.com>,
        Maulik Shah <maulik.shah@....qualcomm.com>,
        Taniya Das <taniya.das@....qualcomm.com>,
        Kamal Wadhwa <kamal.wadhwa@....qualcomm.com>,
        Prudhvi Yarlagadda <quic_pyarlaga@...cinc.com>,
        Qiang Yu <qiang.yu@....qualcomm.com>,
        Manaf Meethalavalappu Pallikunhi <manaf.pallikunhi@....qualcomm.com>,
        Jishnu Prakash <jishnu.prakash@....qualcomm.com>,
        Abel Vesa <abelvesa@...nel.org>
Subject: Re: [PATCH v3 3/4] arm64: dts: qcom: Introduce Glymur base dtsi

On Sat, Dec 20, 2025 at 08:46:31PM +0200, Dmitry Baryshkov wrote:
> On Fri, Dec 19, 2025 at 08:16:56PM +0530, Pankaj Patil wrote:
> > Introduce the base device tree support for Glymur – Qualcomm's
> > next-generation compute SoC. The new glymur.dtsi describes the core SoC
> > components, including:
> > 
> > - CPUs and CPU topology
> > - Interrupt controller and TLMM
> > - GCC,DISPCC and RPMHCC clock controllers
> > - Reserved memory and interconnects
> > - SMMU and firmware SCM
> > - Watchdog, RPMHPD, APPS RSC and SRAM
> > - PSCI and PMU nodes
> > - QUPv3 serial engines
> > - CPU power domains and idle states, plus SCMI/ SRAM pieces for CPU DVFS
> > - PDP0 mailbox, IPCC and AOSS
> > - Display clock controller
> > - SPMI PMIC arbiter with SPMI0/1/2 buses
> > - SMP2P nodes
> > - TSENS and thermal zones (8 instances, 92 sensors)
> > 
> > Add dtsi files for PMH0101, PMK8850, PMCX0102, SMB2370, PMH0104,
> > PMH0110 along with temp-alarm and GPIO nodes needed on Glymur
> > 
> > Add glmur-pmics.dtsi file for all the pmics enabled
> > 
> > Enabled PCIe controllers and associated PHY to support boot to
> > shell with nvme storage,
> > List of PCIe instances enabled:
> > 
> > - PCIe3b
> > - PCIe4
> > - PCIe5
> > - PCIe6
> > 
> > Co-developed-by: Jyothi Kumar Seerapu <jyothi.seerapu@....qualcomm.com>
> > Signed-off-by: Jyothi Kumar Seerapu <jyothi.seerapu@....qualcomm.com>
> > Co-developed-by: Maulik Shah <maulik.shah@....qualcomm.com>
> > Signed-off-by: Maulik Shah <maulik.shah@....qualcomm.com>
> > Co-developed-by: Sibi Sankar <sibi.sankar@....qualcomm.com>
> > Signed-off-by: Sibi Sankar <sibi.sankar@....qualcomm.com>
> > Co-developed-by: Taniya Das <taniya.das@....qualcomm.com>
> > Signed-off-by: Taniya Das <taniya.das@....qualcomm.com>
> > Co-developed-by: Kamal Wadhwa <kamal.wadhwa@....qualcomm.com>
> > Signed-off-by: Kamal Wadhwa <kamal.wadhwa@....qualcomm.com>
> > Co-developed-by: Prudhvi Yarlagadda <quic_pyarlaga@...cinc.com>
> > Signed-off-by: Prudhvi Yarlagadda <quic_pyarlaga@...cinc.com>
> > Co-developed-by: Qiang Yu <qiang.yu@....qualcomm.com>
> > Signed-off-by: Qiang Yu <qiang.yu@....qualcomm.com>
> > Co-developed-by: Abel Vesa <abel.vesa@...aro.org>
> > Signed-off-by: Abel Vesa <abel.vesa@...aro.org>
> > Co-developed-by: Manaf Meethalavalappu Pallikunhi <manaf.pallikunhi@....qualcomm.com>
> > Signed-off-by: Manaf Meethalavalappu Pallikunhi <manaf.pallikunhi@....qualcomm.com>
> > Co-developed-by: Jishnu Prakash <jishnu.prakash@....qualcomm.com>
> > Signed-off-by: Jishnu Prakash <jishnu.prakash@....qualcomm.com>
> > Signed-off-by: Pankaj Patil <pankaj.patil@....qualcomm.com>
> > ---
> >  arch/arm64/boot/dts/qcom/glymur-pmics.dtsi   |   11 +
> >  arch/arm64/boot/dts/qcom/glymur.dtsi         | 5700 ++++++++++++++++++++++++++
> >  arch/arm64/boot/dts/qcom/pmcx0102.dtsi       |  132 +
> >  arch/arm64/boot/dts/qcom/pmh0101.dtsi        |   45 +
> >  arch/arm64/boot/dts/qcom/pmh0104-glymur.dtsi |   83 +
> >  arch/arm64/boot/dts/qcom/pmh0110-glymur.dtsi |   83 +
> >  arch/arm64/boot/dts/qcom/pmk8850.dtsi        |   70 +
> >  arch/arm64/boot/dts/qcom/smb2370.dtsi        |   45 +
> >  8 files changed, 6169 insertions(+)
> > 
> > diff --git a/arch/arm64/boot/dts/qcom/glymur-pmics.dtsi b/arch/arm64/boot/dts/qcom/glymur-pmics.dtsi
> > new file mode 100644
> > index 000000000000..677dd1b74db0
> > --- /dev/null
> > +++ b/arch/arm64/boot/dts/qcom/glymur-pmics.dtsi
> > @@ -0,0 +1,11 @@
> > +// SPDX-License-Identifier: BSD-3-Clause
> > +/*
> > + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
> > + */
> > +
> > +#include "pmk8850.dtsi"		/* SPMI0: SID-0				*/
> > +#include "pmh0101.dtsi"		/* SPMI0: SID-1				*/
> > +#include "pmcx0102.dtsi"	/* SPMI0: SID-2/3	SPMI1: SID-2/3	*/
> > +#include "pmh0110-glymur.dtsi"	/* SPMI0: SID-5/7	SPMI1: SID-5	*/
> > +#include "pmh0104-glymur.dtsi"	/* SPMI0: SID-8/9	SPMI1: SID-11	*/
> > +#include "smb2370.dtsi"		/* SPMI2: SID-9/10/11			*/
> > diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qcom/glymur.dtsi
> > new file mode 100644
> > index 000000000000..eb042541cfe1
> > --- /dev/null
> > +++ b/arch/arm64/boot/dts/qcom/glymur.dtsi
> > @@ -0,0 +1,5700 @@
> > +// SPDX-License-Identifier: BSD-3-Clause
> > +/*
> > + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
> > + */
> > +
> > +#include <dt-bindings/clock/qcom,glymur-dispcc.h>
> > +#include <dt-bindings/clock/qcom,glymur-gcc.h>
> > +#include <dt-bindings/clock/qcom,glymur-tcsr.h>
> > +#include <dt-bindings/clock/qcom,rpmh.h>
> > +#include <dt-bindings/dma/qcom-gpi.h>
> > +#include <dt-bindings/gpio/gpio.h>
> > +#include <dt-bindings/interconnect/qcom,icc.h>
> > +#include <dt-bindings/interconnect/qcom,glymur-rpmh.h>
> > +#include <dt-bindings/interrupt-controller/arm-gic.h>
> > +#include <dt-bindings/mailbox/qcom-ipcc.h>
> > +#include <dt-bindings/phy/phy-qcom-qmp.h>
> > +#include <dt-bindings/power/qcom,rpmhpd.h>
> > +#include <dt-bindings/power/qcom-rpmpd.h>
> > +#include <dt-bindings/soc/qcom,rpmh-rsc.h>
> > +#include <dt-bindings/spmi/spmi.h>
> > +
> > +#include "glymur-ipcc.h"
> 
> What is it and why is it being included this way?
> 

Missed that IPCC headers are defined this way, you can ignore this
comment.

-- 
With best wishes
Dmitry