linux-kernel - Re: [PATCH v3 3/4] arm64: dts: qcom: Introduce Glymur base dtsi

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Message-ID: <5mxpioeokzvn22oirgvp4gwjxvn6acvwfe65sch24fpapklvl2@x2rd3b4nrbx3>
Date: Sun, 21 Dec 2025 17:17:34 +0200
From: Abel Vesa <abel.vesa@....qualcomm.com>
To: Pankaj Patil <pankaj.patil@....qualcomm.com>
Cc: Bjorn Andersson <andersson@...nel.org>,
        Konrad Dybcio <konradybcio@...nel.org>, Rob Herring <robh@...nel.org>,
        Krzysztof Kozlowski <krzk+dt@...nel.org>,
        Conor Dooley <conor+dt@...nel.org>, linux-arm-msm@...r.kernel.org,
        devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
        rajendra.nayak@....qualcomm.com, sibi.sankar@....qualcomm.com,
        Jyothi Kumar Seerapu <jyothi.seerapu@....qualcomm.com>,
        Maulik Shah <maulik.shah@....qualcomm.com>,
        Taniya Das <taniya.das@....qualcomm.com>,
        Kamal Wadhwa <kamal.wadhwa@....qualcomm.com>,
        Prudhvi Yarlagadda <quic_pyarlaga@...cinc.com>,
        Qiang Yu <qiang.yu@....qualcomm.com>,
        Manaf Meethalavalappu Pallikunhi <manaf.pallikunhi@....qualcomm.com>,
        Jishnu Prakash <jishnu.prakash@....qualcomm.com>,
        Abel Vesa <abelvesa@...nel.org>
Subject: Re: [PATCH v3 3/4] arm64: dts: qcom: Introduce Glymur base dtsi

On 25-12-19 20:16:56, Pankaj Patil wrote:
> Introduce the base device tree support for Glymur – Qualcomm's
> next-generation compute SoC. The new glymur.dtsi describes the core SoC
> components, including:
> 
> - CPUs and CPU topology
> - Interrupt controller and TLMM
> - GCC,DISPCC and RPMHCC clock controllers
> - Reserved memory and interconnects
> - SMMU and firmware SCM
> - Watchdog, RPMHPD, APPS RSC and SRAM
> - PSCI and PMU nodes
> - QUPv3 serial engines
> - CPU power domains and idle states, plus SCMI/ SRAM pieces for CPU DVFS
> - PDP0 mailbox, IPCC and AOSS
> - Display clock controller
> - SPMI PMIC arbiter with SPMI0/1/2 buses
> - SMP2P nodes
> - TSENS and thermal zones (8 instances, 92 sensors)
> 
> Add dtsi files for PMH0101, PMK8850, PMCX0102, SMB2370, PMH0104,
> PMH0110 along with temp-alarm and GPIO nodes needed on Glymur
> 
> Add glmur-pmics.dtsi file for all the pmics enabled
> 
> Enabled PCIe controllers and associated PHY to support boot to
> shell with nvme storage,
> List of PCIe instances enabled:
> 
> - PCIe3b
> - PCIe4
> - PCIe5
> - PCIe6
> 
> Co-developed-by: Jyothi Kumar Seerapu <jyothi.seerapu@....qualcomm.com>
> Signed-off-by: Jyothi Kumar Seerapu <jyothi.seerapu@....qualcomm.com>
> Co-developed-by: Maulik Shah <maulik.shah@....qualcomm.com>
> Signed-off-by: Maulik Shah <maulik.shah@....qualcomm.com>
> Co-developed-by: Sibi Sankar <sibi.sankar@....qualcomm.com>
> Signed-off-by: Sibi Sankar <sibi.sankar@....qualcomm.com>
> Co-developed-by: Taniya Das <taniya.das@....qualcomm.com>
> Signed-off-by: Taniya Das <taniya.das@....qualcomm.com>
> Co-developed-by: Kamal Wadhwa <kamal.wadhwa@....qualcomm.com>
> Signed-off-by: Kamal Wadhwa <kamal.wadhwa@....qualcomm.com>
> Co-developed-by: Prudhvi Yarlagadda <quic_pyarlaga@...cinc.com>
> Signed-off-by: Prudhvi Yarlagadda <quic_pyarlaga@...cinc.com>
> Co-developed-by: Qiang Yu <qiang.yu@....qualcomm.com>
> Signed-off-by: Qiang Yu <qiang.yu@....qualcomm.com>
> Co-developed-by: Abel Vesa <abel.vesa@...aro.org>
> Signed-off-by: Abel Vesa <abel.vesa@...aro.org>
> Co-developed-by: Manaf Meethalavalappu Pallikunhi <manaf.pallikunhi@....qualcomm.com>
> Signed-off-by: Manaf Meethalavalappu Pallikunhi <manaf.pallikunhi@....qualcomm.com>
> Co-developed-by: Jishnu Prakash <jishnu.prakash@....qualcomm.com>
> Signed-off-by: Jishnu Prakash <jishnu.prakash@....qualcomm.com>
> Signed-off-by: Pankaj Patil <pankaj.patil@....qualcomm.com>
> ---
>  arch/arm64/boot/dts/qcom/glymur-pmics.dtsi   |   11 +

Separate patch for each file, please.

Abel