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Message-Id: <176651119188.749296.18284396701674542359.b4-ty@kernel.org>
Date: Tue, 23 Dec 2025 23:03:11 +0530
From: Vinod Koul <vkoul@...nel.org>
To: andersson@...nel.org, konradybcio@...nel.org, robh@...nel.org,
krzk+dt@...nel.org, conor+dt@...nel.org, jingoohan1@...il.com,
mani@...nel.org, lpieralisi@...nel.org, kwilczynski@...nel.org,
bhelgaas@...gle.com, johan+linaro@...nel.org, kishon@...nel.org,
neil.armstrong@...aro.org, abel.vesa@...aro.org,
Krzysztof WilczyĆski <kwilczynski@...nel.org>,
Ziyue Zhang <quic_ziyuzhan@...cinc.com>
Cc: linux-arm-msm@...r.kernel.org, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org, linux-pci@...r.kernel.org,
linux-phy@...ts.infradead.org, qiang.yu@....qualcomm.com,
quic_krichai@...cinc.com, quic_vbadigan@...cinc.com
Subject: Re: (subset) [PATCH v7 0/5] pci: qcom: Add QCS8300 PCIe support
On Wed, 25 Jun 2025 17:25:34 +0800, Ziyue Zhang wrote:
> This series depend on the sa8775p gcc_aux_clock and link_down reset change
> https://lore.kernel.org/all/20250529035416.4159963-1-quic_ziyuzhan@quicinc.com/
>
> This series adds document, phy, configs support for PCIe in QCS8300.
> It also adds 'link_down' reset for sa8775p.
>
> Have follwing changes:
> - Add dedicated schema for the PCIe controllers found on QCS8300.
> - Add compatible for qcs8300 platform.
> - Add configurations in devicetree for PCIe0, including registers, clocks, interrupts and phy setting sequence.
> - Add configurations in devicetree for PCIe1, including registers, clocks, interrupts and phy setting sequence.
>
> [...]
Applied, thanks!
[1/5] dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy: Update pcie phy bindings for qcs8300
commit: 393e132efcc5e3fc4ef2bd9bbed2a096096c9359
Best regards,
--
~Vinod
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