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Message-Id: <176651188218.759340.4259216266995514459.b4-ty@kernel.org>
Date: Tue, 23 Dec 2025 23:14:42 +0530
From: Vinod Koul <vkoul@...nel.org>
To: dlan@...too.org, robh@...nel.org, krzk+dt@...nel.org,
conor+dt@...nel.org, kishon@...nel.org, Alex Elder <elder@...cstar.com>
Cc: ziyao@...root.org, aurelien@...el32.net, johannes@...felt.com,
pjw@...nel.org, palmer@...belt.com, aou@...s.berkeley.edu, alex@...ti.fr,
p.zabel@...gutronix.de, guodong@...cstar.com, devicetree@...r.kernel.org,
linux-phy@...ts.infradead.org, spacemit@...ts.linux.dev,
linux-riscv@...ts.infradead.org, linux-kernel@...r.kernel.org
Subject: Re: (subset) [PATCH v7 0/5] Introduce SpacemiT K1 PCIe phy support
On Thu, 18 Dec 2025 09:12:26 -0600, Alex Elder wrote:
> This series introduces a PHY driver to support PCIe on the SpacemiT K1
> SoC. The PCIe controller implementation is derived from a Synopsys
> DesignWare PCIe IP. The PHY driver supports one combination PCIe/USB
> PHY as well as two PCIe-only PHYs. The combo PHY port uses one PCIe
> lane, and the other two ports each have two lanes. All PCIe ports
> operate at 5 GT/second.
>
> [...]
Applied, thanks!
[1/5] dt-bindings: phy: spacemit: Add SpacemiT PCIe/combo PHY
commit: f6194de7df023ecfd5156caf8e2762487be07ef7
[2/5] dt-bindings: phy: spacemit: Introduce PCIe PHY
commit: 326a278a3682d390269699f68e597b5ef5a57d26
[3/5] phy: spacemit: Introduce PCIe/combo PHY
commit: 57e920b92724dd568526990c04e79ed54241c5fc
Best regards,
--
~Vinod
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