| lists.openwall.net | lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC | |
|
Open Source and information security mailing list archives
| ||
|
Message-ID: <176654417344.105270.15876939192797072148.b4-ty@gentoo.org>
Date: Wed, 24 Dec 2025 10:43:34 +0800
From: Yixun Lan <dlan@...too.org>
To: robh@...nel.org,
krzk+dt@...nel.org,
conor+dt@...nel.org,
vkoul@...nel.org,
kishon@...nel.org,
Alex Elder <elder@...cstar.com>
Cc: Yixun Lan <dlan@...too.org>,
ziyao@...root.org,
aurelien@...el32.net,
johannes@...felt.com,
pjw@...nel.org,
palmer@...belt.com,
aou@...s.berkeley.edu,
alex@...ti.fr,
p.zabel@...gutronix.de,
guodong@...cstar.com,
devicetree@...r.kernel.org,
linux-phy@...ts.infradead.org,
spacemit@...ts.linux.dev,
linux-riscv@...ts.infradead.org,
linux-kernel@...r.kernel.org
Subject: Re: (subset) [PATCH v7 0/5] Introduce SpacemiT K1 PCIe phy support
On Thu, 18 Dec 2025 09:12:26 -0600, Alex Elder wrote:
> This series introduces a PHY driver to support PCIe on the SpacemiT K1
> SoC. The PCIe controller implementation is derived from a Synopsys
> DesignWare PCIe IP. The PHY driver supports one combination PCIe/USB
> PHY as well as two PCIe-only PHYs. The combo PHY port uses one PCIe
> lane, and the other two ports each have two lanes. All PCIe ports
> operate at 5 GT/second.
>
> [...]
Applied, thanks!
[4/5] riscv: dts: spacemit: Add a PCIe regulator
https://github.com/spacemit-com/linux/commit/73a6c811fa0d07078c9e1eaecea76ce26fb5f10e
[5/5] riscv: dts: spacemit: PCIe and PHY-related updates
https://github.com/spacemit-com/linux/commit/0be016a4b5d1b927de04e2e7a0a2bce51aacbfff
Best regards,
--
Yixun Lan
Powered by blists - more mailing lists