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Message-ID: <aUo9eiAQ+XMF6zwn@hu-arakshit-hyd.qualcomm.com>
Date: Tue, 23 Dec 2025 12:28:02 +0530
From: Abhinaba Rakshit <abhinaba.rakshit@....qualcomm.com>
To: Konrad Dybcio <konrad.dybcio@....qualcomm.com>
Cc: Bjorn Andersson <andersson@...nel.org>,
Konrad Dybcio <konradybcio@...nel.org>, Rob Herring <robh@...nel.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>, linux-arm-msm@...r.kernel.org,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH] arm64: dts: qcom: monaco: add QCrypto node
On Mon, Dec 22, 2025 at 10:44:49AM +0100, Konrad Dybcio wrote:
> On 12/22/25 8:30 AM, Abhinaba Rakshit wrote:
> > Add Qualcomm Crypto Engine device node for Monaco platform.
> > Bindings and Crypto DMA nodes for the same platform is already
> > present in the tree.
> >
> > QCE and Crypto DMA nodes patch was applied as part of the
> > commit a86d84409947 ("arm64: dts: qcom: qcs8300: add QCrypto nodes"),
> > however was reverted due to compatible string being miss-matched
> > against schema.
> >
> > Resubmitting the enablement of QCE device node for monaco platform
> > with compatible-string being aligned with qcom-qce schema.
> >
> > Signed-off-by: Abhinaba Rakshit <abhinaba.rakshit@....qualcomm.com>
> > ---
> > arch/arm64/boot/dts/qcom/monaco.dtsi | 12 ++++++++++++
> > 1 file changed, 12 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/qcom/monaco.dtsi b/arch/arm64/boot/dts/qcom/monaco.dtsi
> > index 816fa2af8a9a663b8ad176f93d2f18284a08c3d1..dd0b9ea27fe1cdfbf6aba07e98183871be7ee889 100644
> > --- a/arch/arm64/boot/dts/qcom/monaco.dtsi
> > +++ b/arch/arm64/boot/dts/qcom/monaco.dtsi
> > @@ -2350,6 +2350,18 @@ ice: crypto@...8000 {
> > clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>;
> > };
> >
> > + crypto: crypto@...a000 {
> > + compatible = "qcom,qcs8300-qce", "qcom,sm8150-qce", "qcom,qce";
> > + reg = <0x0 0x01dfa000 0x0 0x6000>;
> > + dmas = <&cryptobam 4>, <&cryptobam 5>;
> > + dma-names = "rx", "tx";
> > + iommus = <&apps_smmu 0x480 0x00>,
>
> "0x00" makes no sense - "0x0" is the concise way to write it and
> "0x0000" would be pedantic with the width of the SMR mask field in mind.
>
> Please switch to the former
>
Sure, will update this in patchset v2.
Abhinaba Rakshit
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