linux-kernel - Re: [PATCH V1 3/4] arm64: dts: qcom: hamoa: Add UFS nodes for hamoa SoC

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <986facd7-92e7-4d29-a196-d49cd9f3d35f@oss.qualcomm.com>
Date: Mon, 29 Dec 2025 13:15:26 +0100
From: Konrad Dybcio <konrad.dybcio@....qualcomm.com>
To: Pradeep P V K <pradeep.pragallapati@....qualcomm.com>, vkoul@...nel.org,
        neil.armstrong@...aro.org, robh@...nel.org, krzk+dt@...nel.org,
        conor+dt@...nel.org, martin.petersen@...cle.com, andersson@...nel.org,
        konradybcio@...nel.org, taniya.das@....qualcomm.com,
        dmitry.baryshkov@....qualcomm.com
Cc: linux-arm-msm@...r.kernel.org, linux-phy@...ts.infradead.org,
        devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
        linux-scsi@...r.kernel.org, nitin.rawat@....qualcomm.com
Subject: Re: [PATCH V1 3/4] arm64: dts: qcom: hamoa: Add UFS nodes for hamoa
 SoC

On 12/29/25 7:06 AM, Pradeep P V K wrote:
> Add UFS host controller and PHY nodes for hamoa SoC.
> 
> Signed-off-by: Pradeep P V K <pradeep.pragallapati@....qualcomm.com>
> ---
>  arch/arm64/boot/dts/qcom/hamoa.dtsi | 119 +++++++++++++++++++++++++++-
>  1 file changed, 118 insertions(+), 1 deletion(-)
> 
> diff --git a/arch/arm64/boot/dts/qcom/hamoa.dtsi b/arch/arm64/boot/dts/qcom/hamoa.dtsi
> index bb7c14d473c9..340b907657be 100644
> --- a/arch/arm64/boot/dts/qcom/hamoa.dtsi
> +++ b/arch/arm64/boot/dts/qcom/hamoa.dtsi
> @@ -834,7 +834,10 @@ gcc: clock-controller@...000 {
>  				 <0>,
>  				 <0>,
>  				 <0>,
> -				 <0>;
> +				 <0>,
> +				 <&ufs_mem_phy 0>,
> +				 <&ufs_mem_phy 1>,
> +				 <&ufs_mem_phy 2>;

This patch cannot be applied as-is (needs GCC bindings changes first)
which you didn't mention in the cover letter.

If it were picked up, we'd get DTB valdation errors.

>  
>  			power-domains = <&rpmhpd RPMHPD_CX>;
>  			#clock-cells = <1>;
> @@ -3845,6 +3848,120 @@ pcie4_phy: phy@...e000 {
>  			status = "disabled";
>  		};
>  
> +		ufs_mem_phy: phy@...0000 {
> +			compatible = "qcom,hamoa-qmp-ufs-phy", "qcom,sm8550-qmp-ufs-phy";
> +			reg = <0x0 0x1d80000 0x0 0x2000>;

Please pad the address part to 8 hex digits, so 0x1d80000 -> 0x01d80000

[...]

> +		ufs_mem_hc: ufs@...4000 {
> +			compatible = "qcom,hamoa-ufshc", "qcom,sm8550-ufshc", "qcom,ufshc",
> +				     "jedec,ufs-2.0";

1 a line would be neater, perhaps in the node above too

> +			reg = <0x0 0x1d84000 0x0 0x3000>;

Similar case as before

lgtm otherwise

Konrad