linux-kernel - RE: [PATCH v10 4/4] arm64: dt: imx95: Add the missed ref clock for PCIe[0,1]

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Message-ID:
 <AS8PR04MB8833950FABA4829299CA3D6E8CBCA@AS8PR04MB8833.eurprd04.prod.outlook.com>
Date: Tue, 30 Dec 2025 06:31:47 +0000
From: Hongxing Zhu <hongxing.zhu@....com>
To: Shawn Guo <shawnguo@...nel.org>
CC: "robh@...nel.org" <robh@...nel.org>, "krzk+dt@...nel.org"
	<krzk+dt@...nel.org>, "conor+dt@...nel.org" <conor+dt@...nel.org>,
	"bhelgaas@...gle.com" <bhelgaas@...gle.com>, Frank Li <frank.li@....com>,
	"l.stach@...gutronix.de" <l.stach@...gutronix.de>, "lpieralisi@...nel.org"
	<lpieralisi@...nel.org>, "kwilczynski@...nel.org" <kwilczynski@...nel.org>,
	"mani@...nel.org" <mani@...nel.org>, "s.hauer@...gutronix.de"
	<s.hauer@...gutronix.de>, "kernel@...gutronix.de" <kernel@...gutronix.de>,
	"festevam@...il.com" <festevam@...il.com>, "linux-pci@...r.kernel.org"
	<linux-pci@...r.kernel.org>, "linux-arm-kernel@...ts.infradead.org"
	<linux-arm-kernel@...ts.infradead.org>, "devicetree@...r.kernel.org"
	<devicetree@...r.kernel.org>, "imx@...ts.linux.dev" <imx@...ts.linux.dev>,
	"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>
Subject: RE: [PATCH v10 4/4] arm64: dt: imx95: Add the missed ref clock for
 PCIe[0,1]

> -----Original Message-----
> From: Shawn Guo <shawnguo@...nel.org>
> Sent: 2025年12月30日 11:28
> To: Hongxing Zhu <hongxing.zhu@....com>
> Cc: robh@...nel.org; krzk+dt@...nel.org; conor+dt@...nel.org;
> bhelgaas@...gle.com; Frank Li <frank.li@....com>; l.stach@...gutronix.de;
> lpieralisi@...nel.org; kwilczynski@...nel.org; mani@...nel.org;
> s.hauer@...gutronix.de; kernel@...gutronix.de; festevam@...il.com;
> linux-pci@...r.kernel.org; linux-arm-kernel@...ts.infradead.org;
> devicetree@...r.kernel.org; imx@...ts.linux.dev;
> linux-kernel@...r.kernel.org
> Subject: Re: [PATCH v10 4/4] arm64: dt: imx95: Add the missed ref clock for
> PCIe[0,1]
> 
> On Thu, Dec 11, 2025 at 02:48:21PM +0800, Richard Zhu wrote:
> > i.MX95 PCIes have two reference clock inputs, one of them is from
> > internal PLL. It's wired inside chip and present as "ref" clock. It's
> > not an optional clock.
> >
> > Add the missed ref clock for PCIe[0,1].
> >
> > Signed-off-by: Richard Zhu <hongxing.zhu@....com>
> 
> It doesn't seem to apply to my tree.
Hi Shawn
Thanks for your concerns.
You're right.
I create this patch based on r6.18-rc1. And it wouldn’t be applied to r6.19-rc1.
Please ignore it. Thanks.

Best Regards
Richard Zhu
> 
> Shawn
> 
> > ---
> >  .../boot/dts/freescale/imx95-tqma9596sa-mb-smarc-2.dts | 10
> > ++++++----
> >  1 file changed, 6 insertions(+), 4 deletions(-)
> >
> > diff --git
> > a/arch/arm64/boot/dts/freescale/imx95-tqma9596sa-mb-smarc-2.dts
> > b/arch/arm64/boot/dts/freescale/imx95-tqma9596sa-mb-smarc-2.dts
> > index 5b6b2bb80b288..1258fcb54681e 100644
> > --- a/arch/arm64/boot/dts/freescale/imx95-tqma9596sa-mb-smarc-2.dts
> > +++ b/arch/arm64/boot/dts/freescale/imx95-tqma9596sa-mb-smarc-2.dts
> > @@ -237,8 +237,9 @@ &pcie0 {
> >  	clocks = <&scmi_clk IMX95_CLK_HSIO>,
> >  		 <&pcieclk 1>,
> >  		 <&scmi_clk IMX95_CLK_HSIOPLL_VCO>,
> > -		 <&scmi_clk IMX95_CLK_HSIOPCIEAUX>;
> > -	clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux";
> > +		 <&scmi_clk IMX95_CLK_HSIOPCIEAUX>,
> > +		 <&hsio_blk_ctl 0>;
> > +	clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux", "ref";
> >  	reset-gpio = <&expander2 9 GPIO_ACTIVE_LOW>;
> >  	status = "okay";
> >  };
> > @@ -250,8 +251,9 @@ &pcie1 {
> >  	clocks = <&scmi_clk IMX95_CLK_HSIO>,
> >  		 <&pcieclk 0>,
> >  		 <&scmi_clk IMX95_CLK_HSIOPLL_VCO>,
> > -		 <&scmi_clk IMX95_CLK_HSIOPCIEAUX>;
> > -	clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux";
> > +		 <&scmi_clk IMX95_CLK_HSIOPCIEAUX>,
> > +		 <&hsio_blk_ctl 0>;
> > +	clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux", "ref";
> >  	reset-gpio = <&expander2 10 GPIO_ACTIVE_LOW>;
> >  	status = "okay";
> >  };
> > --
> > 2.37.1
> >