| lists.openwall.net | lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC | |
|
Open Source and information security mailing list archives
| ||
|
Message-ID: <o3jixtcjqbk3i756vy7umb45euu5ofpg4yv2za452xcje5shfa@qgzqnqslxctj>
Date: Tue, 30 Dec 2025 20:09:25 +0200
From: Dmitry Baryshkov <dmitry.baryshkov@....qualcomm.com>
To: Taniya Das <taniya.das@....qualcomm.com>
Cc: Bjorn Andersson <andersson@...nel.org>,
Michael Turquette <mturquette@...libre.com>,
Stephen Boyd <sboyd@...nel.org>, Rob Herring <robh@...nel.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>,
Rajendra Nayak <quic_rjendra@...cinc.com>,
Abel Vesa <abelvesa@...nel.org>,
Konrad Dybcio <konradybcio@...nel.org>,
Bryan O'Donoghue <bryan.odonoghue@...aro.org>,
Ajit Pandey <ajit.pandey@....qualcomm.com>,
Imran Shaik <imran.shaik@....qualcomm.com>,
Jagadeesh Kona <jagadeesh.kona@....qualcomm.com>,
linux-arm-msm@...r.kernel.org, linux-clk@...r.kernel.org,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
Sibi Sankar <sibi.sankar@....qualcomm.com>,
Pradeep P V K <pradeep.pragallapati@....qualcomm.com>
Subject: Re: [PATCH 2/3] clk: qcom: gcc-x1e80100: Add missing UFS symbol mux
clocks
On Tue, Dec 30, 2025 at 11:08:35PM +0530, Taniya Das wrote:
> The UFS symbol RX/TX mux clocks were not defined previously.
> Add these mux clocks so that clock rate propagation reaches
> the muxes correctly.
>
> Fixes: 161b7c401f4b ("clk: qcom: Add Global Clock controller (GCC) driver for X1E80100")
> Signed-off-by: Taniya Das <taniya.das@....qualcomm.com>
> ---
> drivers/clk/qcom/gcc-x1e80100.c | 102 ++++++++++++++++++++++++++++++++++++++--
> 1 file changed, 99 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/clk/qcom/gcc-x1e80100.c b/drivers/clk/qcom/gcc-x1e80100.c
> index e46e65e631513e315de2f663f3dab73e1eb70604..c8fc9e6b1ac97b13f84753ac7f76e23df071c2e0 100644
> --- a/drivers/clk/qcom/gcc-x1e80100.c
> +++ b/drivers/clk/qcom/gcc-x1e80100.c
> @@ -59,6 +59,9 @@ enum {
> DT_USB4_1_PHY_GCC_USB4RTR_MAX_PIPE_CLK,
> DT_USB4_2_PHY_GCC_USB4_PCIE_PIPE_CLK,
> DT_USB4_2_PHY_GCC_USB4RTR_MAX_PIPE_CLK,
> + DT_UFS_PHY_RX_SYMBOL_0_CLK,
> + DT_UFS_PHY_RX_SYMBOL_1_CLK,
> + DT_UFS_PHY_TX_SYMBOL_0_CLK,
> };
>
> enum {
> @@ -103,6 +106,9 @@ enum {
> P_USB4_1_PHY_GCC_USB4RTR_MAX_PIPE_CLK,
> P_USB4_2_PHY_GCC_USB4_PCIE_PIPE_CLK,
> P_USB4_2_PHY_GCC_USB4RTR_MAX_PIPE_CLK,
> + P_UFS_PHY_RX_SYMBOL_0_CLK,
> + P_UFS_PHY_RX_SYMBOL_1_CLK,
> + P_UFS_PHY_TX_SYMBOL_0_CLK,
> };
>
> static struct clk_alpha_pll gcc_gpll0 = {
> @@ -482,6 +488,78 @@ static const struct clk_parent_data gcc_parent_data_33[] = {
> { .index = DT_USB4_2_PHY_GCC_USB4_PCIE_PIPE_CLK },
> };
>
> +static const struct parent_map gcc_parent_map_37[] = {
> + { P_UFS_PHY_RX_SYMBOL_0_CLK, 0 },
> + { P_BI_TCXO, 2 },
> +};
> +
> +static const struct clk_parent_data gcc_parent_data_37[] = {
> + { .index = DT_UFS_PHY_RX_SYMBOL_0_CLK },
> + { .index = DT_BI_TCXO },
> +};
> +
> +static const struct parent_map gcc_parent_map_38[] = {
> + { P_UFS_PHY_RX_SYMBOL_1_CLK, 0 },
> + { P_BI_TCXO, 2 },
> +};
> +
> +static const struct clk_parent_data gcc_parent_data_38[] = {
> + { .index = DT_UFS_PHY_RX_SYMBOL_1_CLK },
> + { .index = DT_BI_TCXO },
> +};
> +
> +static const struct parent_map gcc_parent_map_39[] = {
> + { P_UFS_PHY_TX_SYMBOL_0_CLK, 0 },
> + { P_BI_TCXO, 2 },
> +};
> +
> +static const struct clk_parent_data gcc_parent_data_39[] = {
> + { .index = DT_UFS_PHY_TX_SYMBOL_0_CLK },
> + { .index = DT_BI_TCXO },
> +};
And all of these parent maps and parent data are unused.
> +
> +static struct clk_regmap_phy_mux gcc_ufs_phy_rx_symbol_0_clk_src = {
> + .reg = 0x77064,
> + .clkr = {
> + .hw.init = &(const struct clk_init_data) {
> + .name = "gcc_ufs_phy_rx_symbol_0_clk_src",
> + .parent_data = &(const struct clk_parent_data) {
> + .index = DT_UFS_PHY_RX_SYMBOL_0_CLK,
> + },
> + .num_parents = 1,
> + .ops = &clk_regmap_phy_mux_ops,
> + },
> + },
> +};
> +
> +static struct clk_regmap_phy_mux gcc_ufs_phy_rx_symbol_1_clk_src = {
> + .reg = 0x770e0,
> + .clkr = {
> + .hw.init = &(const struct clk_init_data) {
> + .name = "gcc_ufs_phy_rx_symbol_1_clk_src",
> + .parent_data = &(const struct clk_parent_data) {
> + .index = DT_UFS_PHY_RX_SYMBOL_1_CLK,
> + },
> + .num_parents = 1,
> + .ops = &clk_regmap_phy_mux_ops,
> + },
> + },
> +};
> +
> +static struct clk_regmap_phy_mux gcc_ufs_phy_tx_symbol_0_clk_src = {
> + .reg = 0x77054,
> + .clkr = {
> + .hw.init = &(const struct clk_init_data) {
> + .name = "gcc_ufs_phy_tx_symbol_0_clk_src",
> + .parent_data = &(const struct clk_parent_data) {
> + .index = DT_UFS_PHY_TX_SYMBOL_0_CLK,
> + },
> + .num_parents = 1,
> + .ops = &clk_regmap_phy_mux_ops,
> + },
> + },
> +};
> +
> static struct clk_regmap_phy_mux gcc_usb4_0_phy_dp0_clk_src = {
> .reg = 0x9f06c,
> .clkr = {
> @@ -5148,12 +5226,17 @@ static struct clk_branch gcc_ufs_phy_phy_aux_clk = {
>
> static struct clk_branch gcc_ufs_phy_rx_symbol_0_clk = {
> .halt_reg = 0x7702c,
> - .halt_check = BRANCH_HALT,
> + .halt_check = BRANCH_HALT_DELAY,
> .clkr = {
> .enable_reg = 0x7702c,
> .enable_mask = BIT(0),
> .hw.init = &(const struct clk_init_data) {
> .name = "gcc_ufs_phy_rx_symbol_0_clk",
> + .parent_hws = (const struct clk_hw*[]) {
> + &gcc_ufs_phy_rx_symbol_0_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> .ops = &clk_branch2_ops,
> },
> },
> @@ -5161,12 +5244,17 @@ static struct clk_branch gcc_ufs_phy_rx_symbol_0_clk = {
>
> static struct clk_branch gcc_ufs_phy_rx_symbol_1_clk = {
> .halt_reg = 0x770cc,
> - .halt_check = BRANCH_HALT,
> + .halt_check = BRANCH_HALT_DELAY,
> .clkr = {
> .enable_reg = 0x770cc,
> .enable_mask = BIT(0),
> .hw.init = &(const struct clk_init_data) {
> .name = "gcc_ufs_phy_rx_symbol_1_clk",
> + .parent_hws = (const struct clk_hw*[]) {
> + &gcc_ufs_phy_rx_symbol_1_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> .ops = &clk_branch2_ops,
> },
> },
> @@ -5174,12 +5262,17 @@ static struct clk_branch gcc_ufs_phy_rx_symbol_1_clk = {
>
> static struct clk_branch gcc_ufs_phy_tx_symbol_0_clk = {
> .halt_reg = 0x77028,
> - .halt_check = BRANCH_HALT,
> + .halt_check = BRANCH_HALT_DELAY,
> .clkr = {
> .enable_reg = 0x77028,
> .enable_mask = BIT(0),
> .hw.init = &(const struct clk_init_data) {
> .name = "gcc_ufs_phy_tx_symbol_0_clk",
> + .parent_hws = (const struct clk_hw*[]) {
> + &gcc_ufs_phy_tx_symbol_0_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> .ops = &clk_branch2_ops,
> },
> },
> @@ -7180,6 +7273,9 @@ static struct clk_regmap *gcc_x1e80100_clocks[] = {
> [GCC_USB4_2_TMU_CLK_SRC] = &gcc_usb4_2_tmu_clk_src.clkr,
> [GCC_VIDEO_AXI0_CLK] = &gcc_video_axi0_clk.clkr,
> [GCC_VIDEO_AXI1_CLK] = &gcc_video_axi1_clk.clkr,
> + [GCC_UFS_PHY_RX_SYMBOL_0_CLK_SRC] = &gcc_ufs_phy_rx_symbol_0_clk_src.clkr,
> + [GCC_UFS_PHY_RX_SYMBOL_1_CLK_SRC] = &gcc_ufs_phy_rx_symbol_1_clk_src.clkr,
> + [GCC_UFS_PHY_TX_SYMBOL_0_CLK_SRC] = &gcc_ufs_phy_tx_symbol_0_clk_src.clkr,
> };
>
> static struct gdsc *gcc_x1e80100_gdscs[] = {
>
> --
> 2.34.1
>
--
With best wishes
Dmitry
Powered by blists - more mailing lists